Integrated circuit memory system having dynamic memory bank count and page size
First Claim
1. An integrated circuit memory device, comprising:
- a storage array having a first and second row of storage cells; and
a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein;
during the first mode of operation, the integrated circuit memory device has a first bank count and a first page size, and a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, andduring the second mode of operation, the integrated circuit memory device has a second bank count and a second page size, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers, and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size.
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Accused Products
Abstract
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
154 Citations
31 Claims
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1. An integrated circuit memory device, comprising:
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a storage array having a first and second row of storage cells; and a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein; during the first mode of operation, the integrated circuit memory device has a first bank count and a first page size, and a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, and during the second mode of operation, the integrated circuit memory device has a second bank count and a second page size, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers, and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory system comprising:
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a master device; and an integrated circuit memory device, including; a storage array having a first and second row of storage cells; and a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein; during the first mode of operation, the integrated circuit memory device has a first bank count and a first page size, a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, and during the second mode of operation, the integrated circuit memory device has a second bank count and a second page size, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers, and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for operation of an integrated circuit memory device, comprising:
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in a first operation mode, while providing a first number of memory banks and a first page size, transferring a first plurality of data from a first row of storage cells in a first memory bank to a first plurality of sense amplifiers in a plurality of sense amplifiers; and in a second operation mode, while providing a second number of memory banks and a second page size, transferring a second plurality of data from the first row of storage cells in the first memory bank to the first plurality of sense amplifiers in the plurality of sense amplifiers and simultaneously transferring a third plurality of data from a second row of storage cells in the first memory bank to a second plurality of sense amplifiers in the plurality of sense amplifiers, wherein the second number of memory banks is greater than the first number of memory banks and the first page size is larger than the second page size. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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30. An integrated circuit memory device, comprising:
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a memory bank having a first and second row of storage cells; and means for transferring data to a plurality of sense amplifiers, including; means for transferring in a first operation mode, while providing a first number of memory banks and a first page size, a first plurality of data from the first row of storage cells in the memory bank to a first plurality of sense amplifiers in the plurality of sense amplifiers; and means for transferring in a second operation mode, while providing a second number of memory banks and a second page size, a second plurality of data from the first row of storage cells in the first memory bank to the first plurality of sense amplifiers in the plurality of sense amplifiers and simultaneously transferring a third plurality of data from the second row of storage cells in the first memory bank to a second plurality of sense amplifiers in the plurality of sense amplifiers, wherein the second number of memory banks is greater than the first number of memory banks and the first page size is larger than the second page size. - View Dependent Claims (31)
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Specification