Satellite receiver

• US 7,254,190 B2
• Filed: 09/04/2001
• Issued: 08/07/2007
• Est. Priority Date: 09/01/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.), BayPackets, Inc. (Ribbon Communications, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kwentus, Alan, Jaffe, Steven T., Kaylani, Tarek
• Primary Examiner(s): Ha; Dac V.
• Application Number:
  US09/946,165
• Publication Number:
  US 20020122511A1
• Time in Patent Office: 2,163 Days
• Field of Search: 375/240, 375/254, 375/262, 375/265, 375/285, 375/326, 375/341, 375/373, 375/375, 341/51, 341/52
• US Class Current: 375/340
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0065 Frequency error detectors H04L2027/0067 takes precedence
• CPC Class Codes: H04L 2027/0095 in a preamble or similar structure
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

Systems and techniques for receiving a satellite signal wherein the signal is demodulated and iterative decoded. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A satellite receiver, comprising:

at least one data memory for storing coefficient values generated in accordance with at least one training sequence;

a demodulator configured to demodulate a signal, the demodulator comprising at least one correlator for generating at least one peak correlation value in accordance with the signal and the coefficient values, the demodulator configured to adjust frequency, symbol timing and phase of the signal in accordance with the at least one peak correlation value;

an iterative decoder coupled to the demodulator; and

a second decoder parallel to the iterative decoder coupled to the demodulator, wherein the signal is routed between the iterative decoder and the second decoder based on a coding algorithm of a satellite transmission received by the satellite receiver.

2. The satellite receiver of claim 1 wherein the demodulator comprises a carrier frequency recovery loop configured to track a frequency offset for a signal input to the demodulator.

3. The satellite receiver of claim 2 wherein the demodulator further comprises a multiplier configured to multiply the signal with the frequency offset tracked by the carrier frequency recovery loop.

4. The satellite receiver of claim 2 further comprising a processor configured to compute the frequency offset and load the computed frequency offset into the carrier frequency recovery loop.

5. The satellite receiver of claim 4 wherein the processor comprises a differential correlator configured to compute the frequency offset.

6. The satellite receiver of claim 1 further comprising a processor configured to recover a symbol clock from a signal input to the demodulator.

7. The satellite receiver of claim 6 wherein the demodulator comprises a symbol timing recovery loop configured to track the recovered symbol clock.

8. The satellite receiver of claim 7 wherein the demodulator further comprises a resampler configured to resample the signal with the tracked symbol clock from the symbol timing recovery loop.

9. The satellite receiver of claim 1 wherein the demodulator comprises a phase recovery loop configured to track a phase offset for a signal input to the demodulator.

10. The satellite receiver of claim 9 wherein the demodulator further comprises a multiplier configured to multiply the signal with the phase offset tracked by the phase recovery loop.

11. The satellite receiver of claim 10 further comprising a processor configured to compute the phase offset and load the computed phase offset into the phase recovery loop.

12. The satellite receiver of claim 11 wherein the processor comprises a coherent correlator configured to compute the phase offset.

13. The satellite receiver of claim 1 wherein the second decoder comprises a viterbi decoder.

14. A method of receiving a modulated concatenated encoded signal, comprising:

generating coefficient values in accordance with at least one training sequence;

demodulating the signal comprising;

generating at least one peak correlation value in accordance with the signal and the coefficient values; and

adjusting frequency, symbol timing and phase of the signal in accordance with the at least one peak correlation value; and

routing the signal between an iterative decoder or a non-iterative decoder based on a coding algorithm of a satellite transmission, the non-iterative decoder being coupled in parallel to the iterative decoder.

15. The method of claim 14 wherein the signal demodulation comprises tracking a frequency offset of the signal.

16. The method of claim 15 wherein the signal demodulation further comprises multiplying the signal with the tracked frequency offset.

17. The method of claim 14 further comprising computing a frequency offset of the signal.

18. The method of claim 17 wherein the frequency offset computation comprises computing a plurality of phase differentials from a training sequence embedded in the signal, and correlating the computed phase differentials with a plurality of coefficients.

19. The method of claim 18 wherein the frequency offset computation further comprises computing a frequency error vector as a function of the correlation.

20. The method of claim 18 wherein the phase offset computation further comprises computing a phase error vector as a function of the correlation.

21. The method of claim 14 wherein the signal demodulation comprises recovering a symbol clock from the signal.

22. The method of claim 21 wherein the signal demodulation further comprises resampling the signal with the recovered symbol clock.

23. The method of claim 21 wherein the symbol clock recovery comprises computing a plurality of phase differentials from a training sequence embedded in the signal, and correlating the computed phase differentials with a plurality of coefficients.

24. The method of claim 23 wherein the symbol clock recovery comprises determining a distance in time between at least two correlations, the symbol clock recovery being a function of the distance determination.

25. The method of claim 14 wherein the signal demodulation comprises tracking a phase offset of the signal.

26. The method of claim 25 wherein the signal demodulation further comprises multiplying the signal with the tracked phase offset.

27. The method of claim 25 further comprising computing a phase offset of the signal.

28. The method of claim 27 wherein the phase offset computation comprises correlating a training sequence embedded in the signal with a plurality of coefficients.

29. An integrated circuit, comprising:

a demodulator configured to demodulate a signal, the demodulator comprising;

a carrier frequency recovery loop configured to track a frequency offset for the signal, the carrier frequency recovery loop comprising a multiplier configured to multiply the signal with the frequency offset tracked by the carrier frequency recovery loop;

a symbol timing recovery loop configured to track a symbol clock recovered from the signal, the symbol timing recovery loop comprising a variable interpolator decimator configured to resample the signal with the tracked symbol clock; and

a phase recovery loop configured to track a phase offset for the signal, the phase recovery loop comprising a mixer configured to multiply the signal with the phase offset tracked by the phase recovery loop; and

an iterative decoder coupled to the demodulator.

30. The integrated circuit of claim 29 further comprising at least one processor configured to compute the frequency offset and load the computed frequency offset into the carrier frequency recovery loop.

31. The integrated circuit of claim 30 wherein the at least one processor is configured to compute the phase offset and load the computed phase offset into the phase recovery loop.

32. The integrated circuit of claim 31 wherein the at least one processor comprises a coherent correlator configured to compute the phase offset.

33. The integrated circuit of claim 30 wherein the at least one processor comprises a differential correlator configured to compute the frequency offset.

34. The integrated circuit of claim 29 further comprising a processor configured to compute the phase offset and load the computed phase offset into the phase recovery loop.

35. The integrated circuit of claim 34 wherein the processor comprises a coherent correlator configured to compute the phase offset.

36. The integrated circuit of claim 29 further comprising a second decoder different from the iterative decoder coupled to the demodulator.

37. The integrated circuit of claim 36 wherein the second decoder comprises a viterbi decorder.

38. The integrated circuit of claim 37 wherein the demodulated signal is either provided to the iterative decoder or to the second decoder.

39. The integrated circuit of claim 29 further comprising a feed forward equalizer coupled to receive a signal processed by the variable interpolator decimator.

40. The integrated circuit of claim 39 further comprising a decimation filter coupled to receive an output of the multiplier.

41. The integrated circuit of claim 40 further comprising a Nyquist filter coupled to receive an output of the variable interpolator decimator.

42. The integrated circuit of claim 29 comprising at least one correlator for generating at least one peak correlation value in accordance with the signal and coefficient values generated in accordance with at least one training sequence, the demodulator configured to adjust at least one of frequency, symbol timing and phase of the signal in accordance with the at least one peak correlation value.