Systems and methods for metrology recipe and model generation

• US 7,254,458 B2
• Filed: 06/21/2006
• Issued: 08/07/2007
• Est. Priority Date: 05/04/2001
• Status: Expired due to Fees

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Hasan, Talat Fatima
• Primary Examiner(s): CABRERA, ZOILA E
• Application Number:
  US11/471,992
• Publication Number:
  US 20060247818A1
• Time in Patent Office: 412 Days
• Field of Search: 700/121, 700/108, 700109-110, 702/83, 702/84
• US Class Current: 700/121
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05B 17/02 electric
• CPC Class Codes: G05B 23/0216 Human interface functionality, e.g. monitoring system providing help to the user in the selection of tests or in its configuration

Abstract

Systems and methodologies are disclosed for generating setup information for use measuring process parameters associated with semiconductor devices. A system comprises an off-line measurement instrument to measure an unpatterned wafer and a setup information generator to generate setup information according to the unpatterned wafer measurement. The system then provides the setup information to a process measurement system for use in measuring production wafers in a semiconductor manufacturing process.

Claims

1. A method of evaluating parameters of a semiconductor wafer as part of a manufacturing process comprising the steps of:

measuring a plurality of reference wafers with an off-line scatterometer;

determining the parameters of the reference wafers based on the measurements;

using a model and the results of the determining step, to generate a library of calculated signatures, each corresponding to a different parameter set;

measuring a test wafer with a integrated scatterometer, said integrated scatterometer being integrated with a process tool; and

comparing the results of the measurement of the test wafer to the library of signatures to evaluate the parameters of the test wafer.

2. A method as recited in claim 1, wherein the parameters include critical dimensions.

3. A method as recited in claim 1, wherein the parameters include overlay registration.

4. A method as recited in claim 1, wherein the parameters include the temperature uniformity of a bake process step.

5. A lithograph track processing apparatus comprising:

a stand-alone scatterometer, said scatterometer for measuring reference wafers and based on the measurements generating information corresponding to one of a measurement recipe and a library of signatures corresponding to parameter sets; and

a scatterometer integrated with a lithographic track processing tool, said integrated scatterometer for measuring a test wafer and evaluating process parameters of the test wafer using the measurement of the test wafer and said information received from the stand-alone tool.

6. An apparatus as recited in claim 5, wherein the parameters include critical dimensions.

7. An apparatus as recited in claim 5, wherein the parameters include overlay registration.

8. An apparatus as recited in claim 5, wherein the parameters include the temperature uniformity of a bake process step.

9. An apparatus as recited in claim 5, wherein said stand-alone scatterometer and said integrated scatterometer are connected by a network.

10. A lithograph track processing apparatus comprising:

a stand-alone scatterometer, said scatterometer for measuring reference wafers and using the measurements and a model, to generate a library of calculated signatures each corresponding to a different parameter set; and

a scatterometer integrated with a lithographic track processing tool, said integrated scatterometer for measuring a test wafer and evaluating process parameters of test wafer based on the measurement of the test wafer and the library received from the stand-alone scatterometer.

11. An apparatus as recited in claim 10, wherein the parameters include critical dimensions.

12. An apparatus as recited in claim 10, wherein the parameters include overlay registration.

13. An apparatus as recited in claim 10, wherein the parameters include the temperature uniformity of a bake process step.

14. An apparatus as recited in claim 10, wherein said stand-alone scatterometer and said integrated scatterometer are connected by a network.