Network for decreasing transmit link layer core speed

• US 7,254,647 B2
• Filed: 03/23/2001
• Issued: 08/07/2007
• Est. Priority Date: 03/23/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mann, Gregory J.
• Primary Examiner(s): Flynn; Nathan J.
• Assistant Examiner(s): Joo; Joshua
• Application Number:
  US09/816,967
• Publication Number:
  US 20040210687A1
• Time in Patent Office: 2,328 Days
• Field of Search: 709/213, 709/214, 709/225, 709/229, 709/232, 709/233, 709/234, 709/235, 709/250, 710 51- 52, 710/60, 710 71- 72
• US Class Current: 709/250
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to the transmission media, at least one selector connected to the serial lanes for supporting at least two differing data widths. The logic layer controls the selector, and multiple buffers are interposed in the serial lanes. The selector enables the speed reductions is the upper link layer of the processor. The processor is particularly applicable to interface components used in InfiniBand-type hardware.

Claims

1. A core for providing communications between a transmission media and a processor in a parallel serial architecture, said core comprising:

serial data lanes connecting said processor to said transmission media; and

at least one selector connected to said serial data lanes,

wherein said transmission media and said processor have different operating speeds, and

whereby said selector selectively engages different numbers of said serial data lanes to alter a speed of data passing through said core such that said selector is adapted to perform a speed reduction to accommodate said different operating speeds of said transmission media and said processor,

wherein each of said serial data lanes includes a buffer that corrects for frequency deviations in said transmission media and modifies the frequency of signals in said serial data lanes.

2. The core in claim 1, further comprising a data controller for controlling an operation of said selector.

3. The core in claim 1, wherein said buffer comprise elastic first in, first out (FIFO) buffer.

4. The core in claim 1, wherein said selector comprises a multiplexer.

5. The core in claim 1, wherein additional speed adjustment is attained by said selector engaging additional lanes.

6. A parallel-serial communication system comprising:

at least one processor;

at least one transmission media connecting said at least one processor, wherein said transmission media and said processor have different operating speeds; and

a core between each processor and said transmission media, said core providing communications between said transmission media and said processor, and said core comprising;

serial data lanes connecting said processor to said transmission media; and

at least one selector connected to said serial data lanes,

whereby said selector selectively engages different numbers of said serial data lanes to alter a speed of data passing through said core such that said selector is adapted to perform a speed reduction to accommodate said different operating speeds of said transmission media and said processor, wherein each of said serial data lanes includes a buffer that corrects for frequency deviations in said transmission media and modifies the frequency of signals in said serial data lanes.

7. The parallel-serial communication system in claim 6, further comprising a data controller for controlling an operation of said selector.

8. The parallel-serial communication system in claim 6, wherein said buffer comprise elastic first in, first out (FIFO) buffer.

9. The parallel-serial communication system in claim 6, wherein said selector comprises a multiplexer.

10. The parallel-serial communication system in claim 6, wherein additional speed adjustment is attained by said selector engaging additional lanes.

11. A core for providing communications between a transmission media and a processor in a byte stripped parallel serial InfiniBand architecture, said core comprising:

serial data lanes connecting said processor to said transmission media; and

at least one selector engages different numbers of said serial data lanes to alter a speed of data passing through said core such that said selector is adapted to perform a speed reduction to accommodate said different operating speeds of said transmission media and said processor,

wherein each of said serial data lanes includes a buffer that corrects for frequency deviations in said transmission media and modifies the frequency of signals in said serial data lanes.

12. The core in claim 11, further comprising a data controller for controlling an operation of said selector.

13. The core in claim 11, wherein said buffer comprise elastic first in, first out (FIFO) buffer.

14. The core in claim 11, wherein said selector comprises a multiplexer.

15. The core in claim 11, wherein additional speed adjustment is attained by said selector engaging additional lanes.