Method and system for reducing latency in transferring captured image data by utilizing burst transfer after threshold is reached

• US 7,254,665 B2
• Filed: 06/16/2004
• Issued: 08/07/2007
• Est. Priority Date: 06/16/2004
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Yee, Dawson L.
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US10/870,778
• Publication Number:
  US 20050283544A1
• Time in Patent Office: 1,147 Days
• Field of Search: 710/5, 710/35, 345/156, 345/163, 345/173, 345/346, 715/861, 715/863, 715/865, 715/769
• US Class Current: 345/557
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0421 by interrupting or reflecting a light beam, e.g. optical touch-screen

Abstract

Video sensor data are communicated to a memory of a computer system with reduced latency. Upon receiving data from the video sensor, the data are stored until a desired transfer quantity is reached. The transfer quantity is equivalent to a width of a system memory or cache. When the number of data readings detected reaches an integer multiple of the transfer quantity, a bus request is issued. When the request is granted, the data readings are transferred to system memory in a burst mode. Because the transfer quantity is equivalent to a width of a system memory or cache, at least one line of memory or cache is filled during the course of the transfer. Thus, efficient use is made of bus resources. Also, because the processor can access a full line of system memory or cache without waiting for an additional fetch operation, processor resources are used efficiently.

Claims

1. A method for communicating information to a system memory of a computer system over a bus, the method comprising the steps of:

(a) receiving a plurality of input signals at each of a plurality of cells in a sensor array, the sensor array being positioned to monitor an area of interest;

(b) generating analog output signals for each of the plurality of cells, a magnitudes of each of the analog output signals representing a magnitude of each of the plurality of input signals;

(c) digitizing each of the plurality of analog output signals into a plurality of data readings, a value of each of the plurality of data readings being representative of the magnitude of each of the plurality of analog output signals;

(d) storing the data readings in a storage area;

(e) tracking a number of the data readings stored;

(f) requesting access to the bus when the number of data readings stored reaches a transfer quantity, the transfer quantity being equal to an integer multiple of a system cache width; and

(g) transferring the transfer quantity of data readings over the bus to the system memory in a burst mode upon being granted access to the bus.

2. The method of claim 1, wherein the sensor array comprises an array of sensors responsive to at least one of visible spectrum light signals and non-visible spectrum light signals.

3. The method of claim 1, wherein for each of the data readings, further comprising the step of receiving at least one additional signal, the additional signal providing identifying information about a nature of the data readings.

4. The method of claim 3, wherein the additional signal includes a timing signal indicating an end of a frame.

5. The method of claim 1, wherein the data readings are stored in a storage area comprising a system cache.

6. The method of claim 1, wherein the storage area includes a primary storage area and a secondary storage area, and the data readings are directed to the secondary storage area when the primary storage area stores at least an integer multiple of the transfer quantity of storage bytes.

7. The method of claim 1, wherein the bus is one of a peripheral component interface bus, a peripheral component interface express bus, and an accelerated graphics port bus.

8. The method of claim 1, wherein the transfer quantity is established such that the data readings for the area of interest comprise an integer number of transfer quantities.

9. The method of claim 1, further comprising the step of generating a processor interrupt after transferring a plurality of transfer quantities of data readings such that the plurality of transfer quantities represents a set of data for all of the area of interest.