Pipelined semiconductor memories and systems

• US 7,254,690 B2
• Filed: 05/20/2004
• Issued: 08/07/2007
• Est. Priority Date: 06/02/2003
• Status: Active Grant

• Current Assignee: S Aqua Semiconductor LLC (Intellectual Ventures LLC)
• Original Assignee: S Aqua Semiconductor LLC (Intellectual Ventures LLC)
• Inventors: Rao, G.R. Mohan
• Primary Examiner(s): Elmore; Stephen C.
• Assistant Examiner(s): KIM, DANIEL Y
• Application Number:
  US10/850,719
• Publication Number:
  US 20040243781A1
• Time in Patent Office: 1,174 Days
• Field of Search: 711/169, 711/167, 711/170, 711/100, 710/1, 710/3, 710/4, 710/26, 365/230.01, 365/230.03, 365/230.04, 365/230.09
• US Class Current: 711/169
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Claims

1. A semiconductor memory device, comprising:

a plurality of independently addressable banks for storing data;

a Global Address Supervisor coupled to said plurality of independently addressable banks for storing data, wherein said Global Address Supervisor is configured to continuously receive a sequence of row and column addresses, wherein said continuously received row and column addresses are toggled on both rising and falling edges of a clock signal, wherein said Global Address Supervisor is configured to select one of said plurality of independently addressable banks based on a received row address, wherein said Global Address Supervisor is configured to map said continuously received row and column addresses to a particular bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.

2. The semiconductor memory device as recited in claim 1, wherein if said particular bank of said plurality of independently addressable banks is unavailable, then said Global Address Supervisor is configured to hold an address that is addressable to said particular bank in a staging area.

3. The semiconductor memory device as recited in claim 2, wherein said Global Address Supervisor is further configured to release said address held in said staging area to said particular bank of said plurality of independently addressable banks after said particular bank becomes available.

4. The semiconductor memory device as recited in claim 1, wherein said row and column addresses are received on separate read and write busses.

5. A method for performing address pipelining comprising the steps of:

toggling a continuous sequence of row and column addresses on both rising and falling edges of a clock signal;

receiving said toggled sequence of row and column addresses;

selecting one of a plurality of independently addressable banks for storing data based on a received row address; and

mapping said received toggled sequence of row and column addresses to a particular bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.

6. The method as recited in claim 5 further comprising the step of:

holding an address that is addressable to said particular bank in a staging area if said particular bank of said plurality of independently addressable banks is unavailable.

7. The method as recited in claim 6 further comprising the step of:

releasing said address held in said staging area to said particular bank of said plurality of independently addressable banks after said particular bank becomes available.

8. The method as recited in claim 5, wherein said row and column addresses are received on separate read and write busses.