Security supervisor governing allowed transactions on a system bus

• US 7,254,716 B1
• Filed: 12/20/2002
• Issued: 08/07/2007
• Est. Priority Date: 02/13/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Giles, Christopher M., Bewick, Simon, Williams, Kalvin E.
• Primary Examiner(s): Moise; Emmanuel L.
• Assistant Examiner(s): LOVING, JARIC E
• Application Number:
  US10/324,976
• Time in Patent Office: 1,691 Days
• Field of Search: 725/25, 713/189, 380/210, 380/211, 380/240, 380/241, 380/242, 726/26, 726/27, 726/28, 726/29, 726/30
• US Class Current: 713/189
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect

Abstract

A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.

Claims

1. A circuit comprising:

a plurality of master modules each capable of being a master of a bus; and

a supervisor module configured to (i) detect a target address of a transaction initiated on said bus by a particular master module of said master modules, (ii) identify a predetermined authorization of said transaction in response to (a) an identity of said particular master module, (b) said target address and (c) a current security mode of at least three security modes and (iii) subvert said transaction in response to said predetermined authorization restricting said transaction.

2. The circuit according to claim 1, wherein said supervisor module is further configured to identify said predetermined authorization in further response to a parameter defining which of a plurality of targets may be written to by said master modules.

3. The circuit according to claim 1, wherein said target address comprises an absolute address.

4. The circuit according to claim 1, wherein said supervisor module is further configured to transmit a ready signal in an active state to said particular master module via said bus in response to said predetermined authorization restricting said transaction.

5. The circuit according to claim 1, wherein said supervisor module is further configured to transmit a read command in an inactive state to a target at said target address via said bus in response to (i) said transaction comprising a read transaction and (ii) said predetermined authorization restricting said read transaction.

6. The circuit according to claim 5, wherein said supervisor module is further configured to transmit a predetermined data value to said particular master module via said bus in response to (i) said transaction comprising a read transaction and (ii) said predetermined authorization restricting said read transaction.

7. The circuit according to claim 1, wherein said supervisor module is further configured to transmit a write command in an inactive state to a target at said target address via said bus in response to (i) said transaction comprising a write transaction and (ii) said predetermined authorization restricting said write transaction.

8. The circuit according to claim 7, wherein said supervisor module is further configured to transmit a ready signal to said particular master module via said bus in response to predetermined authorization restricting said write transaction.

9. The circuit according to claim 1, further comprising:

a first memory isolated from said bus; and

a second memory accessible from said bus, wherein said supervisor module is further configured to subvert an instruction fetch type of said transaction initiated from said particular master module to said second memory while permitting said instruction fetch initiated from said particular master module to said first memory.

10. The circuit according to claim 1, wherein (i) said master modules, said supervisor module and a first memory target of a plurality of targets are part of a first chip, (ii) a second memory target of said targets is part of a second chip and (iii) a third memory target of said targets is part of a third chip packaged with said first chip.

11. The circuit according to claim 1, further comprising a programmable read-only memory for storing said predetermined authorization.

12. A method of operating a circuit, comprising the steps of:

(A) detecting a target address of a transaction initiated on a bus by a particular master module of a plurality of master modules each capable of being a master of said bus;

(B) identifying a predetermined authorization of said transaction in response to (i) an identity of said particular master module, (ii) said target address and (iii) a current security mode of at least three security modes; and

(C) subverting said transaction in response to said predetermined authorization restricting said transaction.

13. The method according to claim 12, wherein step (B) identifies said predetermined authorization in further response to a parameter defining which of a plurality of targets may be written to by said master modules.

14. The method according to claim 12, further comprising the step of:

transmitting a read command in an inactive state to a target at said target address via said bus in response to (i) said transaction comprising a read transaction and (ii) said predetermined authorization restricting said read transaction.

15. The method according to claim 14, further comprising the step of:

transmitting a ready signal in an active state to said particular master module via said bus in response to said predetermined authorization restricting said transaction.

16. The method according to claim 15, further comprising the step of:

transmitting a predetermined data value to said particular master module via said bus in response to (i) said transaction comprising a read transaction and (ii) said predetermined authorization restricting said transaction.

17. The method according to claim 12, further comprising the step of:

transmitting a write command in an inactive state to a target at said target address via said bus in response to (i) said transaction comprising a write transaction and (ii) said predetermined authorization restricting said write transaction.

18. The method according to claim 17, further comprising the step of:

transmitting a ready signal to said particular master module via said bus in response to predetermined authorization restricting said write transaction.

19. The method according to claim 12, further comprising the step of:

reading said predetermined authorization from a programmable read-only memory.

20. A circuit comprising:

means for detecting a target address of a transaction initiated on a bus by a particular master module of a plurality of master modules each capable of being a master on said bus;

means for identifying a predetermined authorization of said transaction in response to (i) an identity of said particular master module, (ii) said target address and (iii) a current security mode of at least three security modes; and

means for subverting said transaction in response to said predetermined authorization restricting said transaction.