Method and apparatus of automatic power management control for serial ATA device directly attached to SAS/SATA host controller

• US 7,254,732 B2
• Filed: 07/29/2004
• Issued: 08/07/2007
• Est. Priority Date: 06/25/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Day, Brian A., Bashford, Patrick R., Ayyavu, Vetrivel, Viswanathan, Ganesan
• Primary Examiner(s): Trujillo; James K.
• Application Number:
  US10/901,518
• Publication Number:
  US 20050005178A1
• Time in Patent Office: 1,104 Days
• Field of Search: None
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

Claims

1. An apparatus, comprising:

means for determining whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander;

a counter, communicatively coupled to said means for determining, for counting idle time of a Serial ATA interface including said Serial ATA device and said SAS/SATA host controller when said Serial ATA device is directly attached to said SAS/SATA host controller;

a first programmable register holding a first value, said first programmable register communicatively coupled to said counter;

a second programmable register holding a second value, said second programmable register communicatively coupled to said counter;

automatic power management circuitry communicatively coupled to said Serial ATA interface; and

a third programmable register programmed based on input clock to determine frequency of said counter,

wherein said automatic power management circuitry issues a request for Partial power state to a physical layer of said Serial ATA interface when a value of said counter is equal to said first value, and issues a request for Slumber power state to a physical layer of said Serial ATA interface when a value of said counter is equal to said second value.

2. apparatus of claim 1, wherein said means for determining is a block of a PfIY logic of said SAS/SATA host controller.

3. The apparatus of claim 1, wherein said second value is greater than said first value.

4. The apparatus of claim 1, wherein said automatic power management circuitry comprising:

a first OR logic gate receiving BSY Bit, DRQ Bit and ERR Bit as input and outputting a third value indicating said Serial ATA interface being idle or active;

an inverter logic gate receiving said third value as input and outputting a fourth value to power down counter logic comprising said counter, wherein said Serial ATA interface being idle enables said power down counter logic to count down said idle time; and

power down/up circuitry communicatively coupled to said power down counter logic, wherein said power down/up circuitry issues a request for Partial power state to said physical layer of said Serial ATA interface when a value of said counter is equal to said first value and when said Serial ATA device is directly attached to said SAS/SATA host controller, and issues a request for Slumber power state to said physical layer of said Serial ATA interface when a value of said counter is equal to said second value and when said Serial ATA device is directly attached to said SAS/SATA host controller.

5. The apparatus of claim 4, wherein when said Serial ATA device is directly attached to said SAS/SATA host controller, a Firmware Forcing Partial Bit enables said power down/up circuitry to issue a request for Partial power state to said physical layer of said Serial ATA interface, and a Firmware Forcing Slumber Bit enables said power down/up circuitry to issue a request for Slumber power state to said physical layer of said Serial ATA interface.

6. apparatus of claim 5, wherein said Firmware Forcing Partial Bit and said Firmware Forcing Slumber Bit are stored in a fourth register.

7. The apparatus of claim 4, wherein said automatic power management circuitry further comprising:

a second OR logic gate receiving said third value, Firmware Forcing WakeUp Bit, and a COMWAKE or COMRESET OOB signal as input, wherein said second OR logic gate outputs a WakeUp signal for disabling a power down request to said power down/up circuitry when said third value indicates said Serial ATA interface is active, said Firmware Forcing WakeUp Bit is written in said automatic power management circuitry, and/or said COMWAKE or COMRESET OOB signal is detected;

wherein said power down/up circuitry de-asserts a power down request when said power down/up circuitry receives said WakeUp signal.