Timing performance analysis
First Claim
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1. A method for determining timing performance, comprising:
- obtaining clock-to-output times for a processor core;
using static timing analysis to determine timing data for a memory controller;
obtaining setup and hold times from the timing data for the memory controller;
providing a programmatic representation of logic and interconnects for coupling the memory controller and the processor core;
simulating the programmatic representation of logic and interconnects to obtain delay times;
inputting the delay times, the setup and hold times and the clock-to-output times to a spreadsheet; and
determining path times from the spreadsheet.
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Abstract
Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.
105 Citations
16 Claims
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1. A method for determining timing performance, comprising:
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obtaining clock-to-output times for a processor core; using static timing analysis to determine timing data for a memory controller; obtaining setup and hold times from the timing data for the memory controller; providing a programmatic representation of logic and interconnects for coupling the memory controller and the processor core; simulating the programmatic representation of logic and interconnects to obtain delay times; inputting the delay times, the setup and hold times and the clock-to-output times to a spreadsheet; and determining path times from the spreadsheet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for determining timing performance, comprising:
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obtaining setup and hold times for a processor core; using static timing analysis to determine timing data for a memory controller; obtaining clock-to-output times from the timing data for the memory controller; providing a programmatic representation of logic and interconnects for coupling the memory controller and the processor core; simulating the programmatic representation of logic and interconnects to obtain delay times; inputting the delay times, the setup and hold times and the clock-to-output times to a spreadsheet; and determining path times from the spreadsheet. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification