System and apparatus for using test structures inside of a chip during the fabrication of the chip
First Claim
1. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:
- locating one or more test structures in a die on the wafer, wherein each of the one or more test structures are configured to provide electrical activity when activated, wherein the electrical activity is indicative of a quality metric of the fabrication sequence and/or of a particular fabrication step or sequence in the fabrication;
subjecting the wafer to at least one of a plurality of fabrication processes that comprise the fabrication;
activating the one or more test structures using one or more external sources, so as to generate one or more signals from within the die;
measuring electrical activity that is invariant and provided by the at least one or more test structures in order to determine a performance parameter value of the one or more test structures; and
using a correlation between the particular fabrication step or sequence of the die and the performance parameter value of each of the one or more test structures to evaluate the fabrication.
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Accused Products
Abstract
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
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Citations
31 Claims
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1. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:
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locating one or more test structures in a die on the wafer, wherein each of the one or more test structures are configured to provide electrical activity when activated, wherein the electrical activity is indicative of a quality metric of the fabrication sequence and/or of a particular fabrication step or sequence in the fabrication; subjecting the wafer to at least one of a plurality of fabrication processes that comprise the fabrication; activating the one or more test structures using one or more external sources, so as to generate one or more signals from within the die; measuring electrical activity that is invariant and provided by the at least one or more test structures in order to determine a performance parameter value of the one or more test structures; and using a correlation between the particular fabrication step or sequence of the die and the performance parameter value of each of the one or more test structures to evaluate the fabrication. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification