Structure and method to induce strain in a semiconductor device channel with stressed film under the gate

• US 7,256,081 B2
• Filed: 02/01/2005
• Issued: 08/14/2007
• Est. Priority Date: 02/01/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhu, Huilong
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Pham; Thanh V.
• Application Number:
  US10/906,054
• Publication Number:
  US 20060172500A1
• Time in Patent Office: 924 Days
• Field of Search: 438/184, 438/230, 257/69, 257/204, 257/900, 257/E29.26
• US Class Current: 438/184
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

Claims

1. A method of manufacturing a CMOS device with a stressed channel, comprising the steps of:

forming a silicon island comprising a top surface and multiple sidewalls;

forming a gate structure comprising at least a gate oxide and a gate stack on the top surface, the gate structure extending beyond a sidewall of the silicon island; and

surrounding a portion of the silicon island around the multiple sidewalls with a stress film.

2. The method of claim 1, further comprising surrounding substantially all of the silicon island around the multiple sidewalls with the stress film.

3. The method of claim 1, further comprising arranging the stress film to extend from a first side of the gate oxide to a second side of the gate oxide below the gate stack along a sidewall of the silicon island.

4. The method of claim 1, further comprising arranging the stress film to cover the gate structure of the CMOS device.

5. The method of claim 1, further comprising configuring the stress film to create a stress in the stressed channel with a direction approximately orthogonal to the top surface of the silicon island, along with a stress in the direction parallel to the top surface of the silicon island.

6. The method of claim 1, further comprising configuring the stress film to comprise Si₃N₄.

7. The method of claim 1, further comprising etching a tunnel under the gate stack adjacent a sidewall of the silicon island.