Display device having a structure for preventing the deterioration of a light emitting device

• US 7,256,421 B2
• Filed: 05/14/2003
• Issued: 08/14/2007
• Est. Priority Date: 05/17/2002
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Takayama, Toru, Murakami, Satoshi, Yamazaki, Shunpei
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US10/437,446
• Publication Number:
  US 20040080263A1
• Time in Patent Office: 1,553 Days
• Field of Search: 257/59, 257/72, 257/637, 257347-354
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133305 Flexible substrates, e.g. plastics, organic film
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H05B 33/04 Sealing arrangements , e.g. against humidity
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 50/84 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/87 Passivation; Containers; Encapsulations

Abstract

A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements'"'"' (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.

Claims

1. A display device comprising:

a first semiconductor and a second semiconductor on an insulating surface;

a gate insulating film over the first semiconductor;

a first metal layer over the gate insulating film;

a passivation film over the first metal layer;

a second metal layer over the passivation film;

a flattening film over the second metal layer;

a barrier film over the flattening film;

a third metal layer over the barrier film;

the gate insulating film over the second semiconductor;

a fourth metal layer over the gate insulating film;

the passivation film over the fourth metal layer;

a fifth metal layer over the passivation film;

the flattening film over the fifth metal layer;

a sixth metal layer over the barrier film;

wherein a first opening formed in the flattening film is covered by the barrier film;

wherein a second opening is formed inside side faces of the first opening, the second opening being formed in a lamination having the gate insulating film, the passivation film, and the barrier film;

wherein the third metal layer is connected to the first semiconductor via the first opening and the second opening;

wherein a first capacitor element comprises the second semiconductor, the gate insulating film, and the metal layer; and

wherein a second capacitor element comprises the fourth metal layer, the passivation film, and the fifth metal layer.

2. A display device comprising:

a first semiconductor and a second semiconductor on an insulating surface;

a gate insulating film over the first semiconductor;

a first metal layer over the gate insulating film;

a passivation film over the first metal layer;

a second metal layer over the passivation film;

a flattening film aver the second metal layer;

a barrier film over the flattening film;

a third metal layer over the barrier film;

the gate insulating film over the second semiconductor;

a fourth metal layer over the gate insulating film;

the passivation film over the fourth metal layer;

a fifth metal layer over the passivation film;

the flattening film over the fifth metal layer;

a sixth metal layer over the barrier film;

wherein a second opening is formed inside side faces of the first opening, the second opening being formed in a lamination having the gate insulating film, the passivation film, and the barrier film; and

wherein the third metal layer is connected to the first semiconductor via the first opening and the second opening;

wherein a first capacitor element comprises the second semiconductor, the gate insulating film, and the fourth metal layer;

wherein a second capacitor element comprises the fourth metal layer, the passivation film, and the fifth metal layer; and

wherein a third capacitor element comprises the fifth metal layer, the barrier film, and the sixth metal layer.

3. A display device comprising:

a first semiconductor and a second semiconductor on an insulating surface;

a gate insulating film over the first semiconductor;

a first metal layer over the gate insulating film;

a passivation film over the first semiconductor;

a second metal layer over the passivation film;

a flattening film over the second metal layer;

a barrier film over the flattening film;

a third metal layer over the barrier film;

the gate insulating film over the second semiconductor;

a fourth metal layer over the gate insulating film;

the passivation film over the fourth metal layer;

a fifth metal layer over the passivation film;

the flattening film over the fifth metal layer;

a sixth metal layer over the barrier film;

wherein a first opening formed in the flattening film is covered by the barrier film;

wherein a second opening is formed inside side faces of the first opening, the second opening being formed in a lamination having the gate insulating film, the passivation film, and the barrier film; and

wherein the third metal layer is connected to the first semiconductor via the first opening and the second opening;

wherein a capacitor element comprises the fourth metal layer, the passivation film, and the fifth metal layer.

4. A display device according to claim 3, wherein the first metal layer is formed by stacking a tantalum nitride film and a tungsten film.

5. A display device according to claim 3, wherein the second metal layer is formed of an aluminum film or a thin copper film.

6. A display device according to claim 3, wherein the third metal layer is formed by stacking a titanium film, a titanium nitride film, and an aluminum film.

7. A display device according to claim 3, wherein the barrier film is formed of a silicon nitride film having an etching rate of at most 9 nm/min.

8. A display device according to claim 3, wherein the barrier film is formed of a silicon nitride film having hydrogen concentration of at most 1×

10²¹ cm<sup>−

3</sup>.

9. A display device according to claim 3, wherein the barrier film is formed of a silicon nitride film having an etching rate of at most 9 nm/min and hydrogen concentration of at most 1×

10²¹ cm<sup>−

3</sup>.

10. A display device according to claim 3, wherein the barrier film is formed of a silicon nitride film having hydrogen concentration of at most 1×

10²¹ cm<sup>−

3</sup> and oxygen concentration ranging from 5×

10¹⁸ to 5×

10²¹ cm<sup>−

3</sup>.

11. A display device according to claim 3, wherein the barrier film is formed of a silicon nitride film having an etching rate of at most 9 nm/min, hydrogen concentration of at most 1×

10²¹ cm<sup>−

3</sup>, and oxygen concentration ranging from 5×

10¹⁸ to 5×

10²¹ cm<sup>−

3</sup>.

12. A display device according to claim 7, wherein the silicon nitride film is controlled back pressure thereof at most 1×

10<sup>−

3</sup> Pa by a turbo-molecular pump or a cryopump, and formed by sputtering silicon single crystal target using N₂ gas or mixed gas of N₂ gas and rare gas.