Memory cell with buffered-layer

• US 7,256,429 B2
• Filed: 12/21/2005
• Issued: 08/14/2007
• Est. Priority Date: 01/12/2004
• Status: Expired due to Term

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Zhang, Fengyan, Hsu, Sheng Teng, Li, Tingkai, Evans, David R., Pan, Wei, Zhuang, Wei-Wei, Tajiri, Masayuki
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/314,222
• Publication Number:
  US 20060099724A1
• Time in Patent Office: 601 Days
• Field of Search: 257/536, 257/53, 257/108, 438/3, 365/100, 365/157, 365/158
• US Class Current: 257/108
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/51 Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
• CPC Class Codes: G11C 2213/56 Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/801 Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa₂Cu₃O_7−X (YBCO), indium oxide (In₂O₃), or ruthenium oxide (RuO₂), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr_1−XCa_XMnO₃ (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Claims

1. A method for forming an RRAM buffered-layer memory cell, the method comprising:

forming a CMOS transistor with source and drain active regions;

forming a metal interlevel interconnect to a transistor active region;

forming a bottom electrode overlying the interlevel interconnect;

forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode;

forming a memory-stable semiconductor buffer layer overlying the memory film; and

,

forming a top electrode overlying the semiconductor buffer layer.

2. A method for programming a buffered-layer memory cell using bipolar and uni-polar pulses, the method comprising:

applying a first voltage pulse with a first polarity to a memory cell top electrode;

in response to the first pulse, creating a low resistance in a colossal magnetoresistance (CMR) memory film, buffered from the top electrode by a memory-stable semiconductor region;

applying a second voltage pulse with a second polarity, opposite of the first polarity, to the memory cell top electrode;

in response to the second pulse, creating a high resistance in the CMR memory film;

applying a third pulse, having a polarity selected from the group including the first and second polarities, and a pulse width of greater than 5 microseconds; and

,

in response to the third pulse, creating a low resistance in the CMR memory film.

3. The method of claim 2 wherein creating a low resistance in the CMR memory film in response to the first pulse includes creating a resistance in the range of 1000 to 10 k ohms;

and,

wherein creating a high resistance in the CMR memory film in response to the second pulse includes creating a resistance in the range of 100 k to 10M ohms.

4. The method of claim 3 wherein applying a first pulse with a first polarity to the memory cell top electrode includes applying a voltage pulse with a width in the range of 5 to 500 nanoseconds (ns);

and,

wherein applying a second pulse with a second polarity to the memory cell top electrode includes applying a voltage pulse with a width in the range of 5 to 500 na.

5. The method of claim 4 wherein the CMR film has a thickness in the range of 10 to 200 nanometers;

and,

wherein applying a first pulse with a first polarity to the memory cell top electrode includes applying a pulse with a voltage amplitude in the range of 2 to 6 volts; and

,

wherein applying a second pulse with a second polarity to the memory cell top electrode includes applying a pulse with a voltage amplitude in the range of 2 to 6 volts.

6. A buffered-layer memory cell comprising:

a bottom electrode;

a colossal magnetoresistance (CMR) memory film overlying the bottom electrode;

a memory-stable semiconductor buffer layer overlying the CMR memory film; and

,

a top electrode overlying the semiconductor buffer layer.

7. The memory cell of claim 6 wherein bottom electrode has an area;

and,

wherein the top electrode has an area approximately equal to the bottom electrode area.

8. The memory cell of claim 6 wherein the CMR memory film has a thickness in the range of 10 to 200 nanometers (nm).

9. The memory cell of claim 6 wherein the semiconductor buffer layer is formed from a metal oxide material.

10. The memory cell of claim 6 wherein the semiconductor buffer layer is formed from a material selected from the group including YBa2Cu3O7-X (TBCO), indium oxide (In2O3), and ruthenium oxide (RuO2).

11. The memory cell of claim 6 wherein the bottom electrode is formed from a material selected from the group including TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, and PtIrOx compounds;

and,

wherein the top electrode is formed from a material selected from the group including TiN, TiN/Pt, TiN/In, PtRhOx compounds, and PtIrOx compounds.

12. The memory cell of claim 6 wherein the CMR memory film is formed from Pr₁₋

XCa_XMnO₃ (PCMO), where x is in the region between 0.1 and 0.6.

13. The memory cell of claim 6 wherein the CMR film has an area approximately equal to the bottom electrode area.

14. The memory cell of claim 10 wherein the semiconductor buffer layer has a thickness in the range of 10 to 200 nm.

15. An RRAM buffered-layer memory cell comprising:

a CMOS transistor with source and drain active regions;

a metal intorlevel interconnect overlying a transistor active region;

a bottom electrode overlying the interlevel interconnect;

a colossal magnetoresistance (CMR) memory film overlying the bottom electrode;

a memory-stable semiconductor buffer layer overlying the CMR memory film; and

,

a top electrode overlying the semiconductor buffer layer.