Resistance-reduced semiconductor device and methods for fabricating the same
First Claim
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1. A resistance-reduced semiconductor device, comprising:
- a resistance-reduced transistor, comprising;
a gate stack on a silicon-containing substrate;
a pair of source/drain regions in the silicon-containing substrate, oppositely adjacent to the gate stack;
a metallized bilayer overlying each source/drain region to thereby reduce a resistance thereof, wherein the metallized bilayer comprises a metal top layer;
a first dielectric layer having a conductive contact, overlying the resistance-reduced transistor;
a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact electrically form a conductive pathway down to the top metal layer over one of the source/drain regions;
a third dielectric layer having a second conductive feature, overlying the second dielectric layer; and
a first conductive cap layer partially overlying the first conductive feature, wherein the first conductive cap layer exposes a portion of the top surface of the first conductive feature to thereby contact the second conductive feature directly and the first conductive feature.
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Abstract
Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.
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8 Claims
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1. A resistance-reduced semiconductor device, comprising:
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a resistance-reduced transistor, comprising; a gate stack on a silicon-containing substrate; a pair of source/drain regions in the silicon-containing substrate, oppositely adjacent to the gate stack; a metallized bilayer overlying each source/drain region to thereby reduce a resistance thereof, wherein the metallized bilayer comprises a metal top layer; a first dielectric layer having a conductive contact, overlying the resistance-reduced transistor; a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact electrically form a conductive pathway down to the top metal layer over one of the source/drain regions; a third dielectric layer having a second conductive feature, overlying the second dielectric layer; and a first conductive cap layer partially overlying the first conductive feature, wherein the first conductive cap layer exposes a portion of the top surface of the first conductive feature to thereby contact the second conductive feature directly and the first conductive feature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification