Programmable interconnect architecture for programmable logic devices

• US 7,256,613 B1
• Filed: 06/24/2005
• Issued: 08/14/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Sharpe-Geisler, Brad, Agrawal, Om P., Lee, Cindy
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/165,709
• Time in Patent Office: 781 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

In one embodiment of the invention, a programmable logic device (PLD) includes a plurality of programmable logic blocks arrayed in rows and columns, wherein each programmable logic block is coupled to a corresponding vertical routing resource and a corresponding horizontal routing resource, and wherein each vertical and horizontal routing resource includes a plurality of wires organized into wire groups and each programmable logic block has a set of inputs organized into input groups. The PLD also includes a plurality of connection boxes, each connection box corresponding to a programmable logic block and operable to couple a given wire group in one of the corresponding vertical and horizontal routing resources to a given input group independently of whether a given wire group in the remaining one of the corresponding vertical and horizontal routing resources is coupled through the connection box to the given input group.

Claims

1. A programmable logic device, comprising:

a plurality of programmable logic blocks arrayed in rows and columns, wherein each programmable logic block is coupled to a corresponding vertical routing resource and a corresponding horizontal routing resource, and wherein each vertical and horizontal routing resource includes a plurality of wires organized into wire groups and each programmable logic block has a set of inputs organized into input groups; and

a plurality of connection boxes, each connection box corresponding to a programmable logic block and operable to couple a wire group to an input group, wherein a given wire group in one of the corresponding vertical and horizontal routing resources is couplable to a given input group independently of whether a given wire group in the remaining one of the corresponding vertical and horizontal routing resources is also couplable to the given input group.

2. The programmable logic device of claim 1, wherein each horizontal and vertical routing resource is a segmented routing resource.

3. The programmable logic device of claim 1, wherein each programmable logic block comprises a plurality of lookup tables.

4. The programmable logic device of claim 3, wherein each lookup table is a four-input lookup table.

5. The programmable logic device of claim 4, wherein each programmable logic block comprises at least eight lookup tables.

6. The programmable logic device of claim 2, wherein the segmentation of each horizontal and vertical routing resource comprises a segment-0 resource, a segment-1 resource, a segment-2 resource, and a segment-6 resource.

7. The programmable logic device of claim 3, wherein the programmable logic device comprises a field programmable gate array.

8. The programmable logic device of claim 1, further comprising:

a configuration memory operable to store configuration data for configuring the plurality of switch matrices.

9. The programmable logic device of claim 8, wherein the configuration memory is a volatile memory.

10. A programmable logic device, comprising:

a programmable logic block having a set of inputs organized into input groups;

a horizontal routing resource;

a vertical routing resource, wherein the vertical routing resource and horizontal routing resource each includes a plurality of wires organized into wire groups; and

a switch matrix configured to couple a wire group to an input group, wherein a given wire group in the horizontal routing resource is couplable to a given input group independently of whether another wire group in the vertical routing resource is also couplable to the given input group.

11. The programmable logic device of claim 10, wherein the input groups comprise sixteen input groups.

12. The programmable logic device of claim 10, wherein the logic block includes eight four-input lookup tables having their thirty-two inputs organized into sixteen two-input groups.

13. The programmable logic device of claim 10, wherein the horizontal and routing resource is each a segment-2 routing resource having its plurality of wires organized into eight wire groups.

14. The programmable logic device of claim 12, wherein the lookup tables are organized into four slices.

15. A programmable logic device, comprising:

a plurality of vertical routing resources;

a plurality of horizontal routing resources, wherein at least a first one of the horizontal routing resources and at least a first one of the vertical routing resources both include a plurality of wires organized into at least a first wire group and a second wire group;

a first input switch matrix operable to select signals from the first wire group in the first horizontal routing resource and from the first wire group in the first vertical routing resources to provide an input signal to a first lookup table (LUT) input; and

a second input switch matrix operable to select signals from the first wire group in the first horizontal routing resource and from the second wire group in the first vertical routing resource to provide an input signal to a second LUT input.

16. The programmable logic device of claim 15, wherein the first and second input switch matrices comprise multiplexers within a connection box operable to connect a programmable logic block containing LUTs to the horizontal and vertical routing resources.

17. The programmable logic device of claim 15, wherein the plurality of vertical routing resources and the plurality of horizontal routing resources are both segmented routing resources.

18. The programmable logic device of claim 15, wherein the first and second LUT inputs are inputs to a same LUT.

19. The programmable logic device of claim 15, wherein the first and second LUT inputs are inputs to different LUTs.

20. The programmable logic device of claim 15, wherein the first and second wire groups each includes a plurality of wires greater than two.