Programmable display device

• US 7,256,789 B1
• Filed: 01/22/1998
• Issued: 08/14/2007
• Est. Priority Date: 01/23/1997
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakamura, Satoshi, Yamamura, Hiroyuki, Moriya, Masaaki, Yamamoto, Shinzi
• Primary Examiner(s): Nguyen; Kimbinh T.
• Application Number:
  US09/341,633
• Time in Patent Office: 3,491 Days
• Field of Search: 345/560, 345/601, 345/603, 345/604, 345/667, 345/670, 345/538, 345/548, 345/547, 345/669, 345/443, 345/554, 345/544, 345/566, 345/2.2, 345/92, 345/556, 345/503, 345/533, 345/543, 345/542, 345/501, 345/98, 345/530, 345/532, 345/600, 345/605, 710/22, 710/68, 711/170
• US Class Current: 345/530
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

It comprises a main CPU, a main memory for storing the programs, display data and other data, a data processing circuit for performing a processing to convert the display data in the main memory to the data format for the display, a display memory section for storing the converted display data, an output processing circuit for performing a processing to output the display data on the screen, a DMA for performing a data access to the main memory, a program memory, a data memory, a display processor for interpreting the commands/data described in the program memory and the data memory and transferring the display data according thereto, and a sync signal generating circuit.

Claims

1. A programmable display device comprising:

a main memory which stores the display data;

a data processing circuit which converts the data format of said display data into the data format of the screen display;

a number of line memories which store the display data converted by said data processing circuit per unit of the display line;

a display control section which controls the transfer and storage of the display data from said main memory to said line memory and the readout of the necessary display data from said line memory to display it on the screen; and

a main control section which controls the storage of said display data in said main memory, and the transfer of the stored information including the data format and the storage address to said display control section, wherein

said display control section reading out said display data by specifying the address of the display data for one line which has a possibility to be displayed on the screen to said main memory from which the display data is transferred, based on said stored information, causing said data processing circuit to perform the data transfer and select said line memory to store said display data.

2. A programmable display device according to claim 1, wherein said display control section controls the storage of the display data to be utilized repeatedly in said line memory, so that when the repeated display data is displayed, said repeated display data is read out from said line memory by specifying the address thereof and displayed on the screen.

3. A programmable display device according to claim 1, further comprising a data buffer memory for storing the display data to be utilized repeatedly, and when said data is displayed on the screen, said display control section causes said repeated display data to be read out from said data buffer memory and displayed on the screen.

4. A programmable display device according to claim 1, which includes:

a first buffer memory for storing the display data read out from said main memory;

a second buffer memory for storing the display data read out from said first buffer memory; and

an address counter for counting the readout address and the write address of said first and the second buffer memories;

wherein

said display control section controlling the stop and motion of the readout address count and the write address count, respectively, with respect to said address counter, performing the processing of expansion, contraction and skip and storing the data in said line memory.

5. A programmable display device according to claim 4, wherein said display control section causes the stop and motion of the readout address count to be repeated in a predetermined order.

6. A programmable display device according to claim 1, wherein said data processing circuit has a plurality of conversion processing circuits for converting various data formats, and

said display control section selects said conversion processing circuits based on the data format information of said stored information.

7. A programmable display device according to claim 1, wherein said display control section is provided with a program memory and a data memory for storing the necessary programs and data.

8. A programmable display device according to claim 7, wherein said display control section causes the information necessary for said program memory and said data memory to be transferred from said main memory.

9. A programmable display device according to claim 1, wherein said display control section adds the line information showing in which line the data is to be used when storing the display data in said line memory, and controls the display of the data in such a manner that when reading out the display data from said line memory, the line information is read out simultaneously and the data is displayed only when the line which uses said display data is the same with the line information.