Non-volatile memory device, and multi-page program, read and copyback program method thereof

• US 7,257,027 B2
• Filed: 12/06/2005
• Issued: 08/14/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Jin Su
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/295,887
• Publication Number:
  US 20070002621A1
• Time in Patent Office: 616 Days
• Field of Search: 365/185.11, 365/185.12, 365/185.17, 365/185.25
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A NAND-type flash memory device has a multi-plane structure. Page buffers are divided into even page buffers and odd page buffers and are driven at the same time. Cells connected to even bit lines within one page and cell connected to odd bit lines within one page are programmed, read and copyback programmed at the same time.

Claims

1. A non-volatile memory device, comprising:

a cell array having memory cells, each memory cell coupled to a word line and a bit line;

a plurality of even page buffers, each even page buffer coupled to an even bit line of the bit lines via an even sensing line; and

a plurality of odd page buffers, each odd page buffer coupled to an odd bit line of the bit lines via an odd sensing line,

wherein the even page buffers and the odd page buffers sequentially receives data to be programmed, and

wherein the data are programmed at substantially the same time into even memory cells and odd memory cells that are coupled to the same word line.

2. The non-volatile memory device as claimed in claim 1, wherein the cell array comprises a plurality of planes, and each plane includes a plurality of memory cell blocks and the plurality of even and odd page buffers.

3. The non-volatile memory device as claimed in claim 1, wherein the plurality of planes performs a program operation, a read operation, or a copyback program operation at substantially the same time.

4. The non-volatile memory device as claimed in claim 1, wherein each of the plurality of even page buffer includes an even register for storing data for the even bit lines;

and a transistor for selectively coupling the even register and the even bit lines.

5. The non-volatile memory device as claimed in claim 4, wherein the even register comprises:

a latch circuit to latch data;

a precharge unit to precharge the even sensing lines;

a discharge unit to discharge a first node of the latch circuit;

a data I/O unit coupled to the latch circuit to input and output data;

a program unit to program data of the first node of the latch circuit into the memory cells; and

a copyback program unit to copyback program data of a second node of the latch circuit into the memory cells.

6. The non-volatile memory device as claimed in claim 5, wherein the even register further includes a reset unit to initialize the latch circuit and make each of the even bit lines as a shielding bit line in a read operation.

7. The non-volatile memory device as claimed in claim 1, wherein each of the plurality of odd page buffers includes an odd register for storing data for the odd bit lines, and a transistor for selectively coupling the odd register and one of the odd bit lines.

8. The non-volatile memory device as claimed in claim 7, wherein the odd register comprises:

a latch circuit to latch data;

a precharge unit to precharge the even sensing lines;

a discharge unit to discharge a first node of the latch circuit;

a data I/O unit connected to the latch circuit to input and output data;

a program unit to program data of the first node of the latch circuit into the memory cells; and

a copyback program unit to copyback program data of a second node of the latch circuit into the memory cells.

9. The non-volatile memory device as claimed in claim 7, wherein the odd register further includes a reset unit to initialize the latch circuit and make each of the even bit lines as a shielding bit line, in a read operation.

10. A multi-page program method for a non-volatile memory device having a cell array including memory cells coupled to word lines and bit lines, the method:

sequentially storing data to be programmed in a plurality of even page buffers respectively coupled to even bit lines of the bit lines through even sensing lines, and a plurality of odd page buffers respectively coupled to odd bit lines of the bit lines through the odd sensing lines that are separated from the even sensing lines, the even page buffers storing first data and the odd page buffers storing second data; and

programming at substantially the same time the first and second data stored in the even and odd page buffers, respectively, into even memory cells and odd memory cells coupled to the same word line.

11. A multi-page read method for a non-volatile memory device having a cell array including memory cells respectively coupled to word lines and bit lines, the method comprising:

precharging odd bit lines to make the odd bit lines to function as shielding bit lines;

reading first data programmed into even memory cells coupled to a given word line and storing the first data into a plurality of even page buffers;

precharging even bit lines to make the even bit lines to function as shielding bit lines;

reading second data programmed into odd memory cells connected to the given word line and storing the second data in a plurality of odd page buffers; and

sequentially reading and outputting the first and second data stored in each of the plurality of even and odd page buffers.

12. The multi-page read method as claimed in claim 11, wherein in order to make the odd bit line to function as the shielding bit lines, each of the odd sensing lines and the odd bit lines is precharged using each of the odd page buffers.

13. The multi-page read method as claimed in claim 11, wherein in order to make the even bit line to function as the shielding bit lines, each of the even sensing lines and the even bit lines is precharged using each of the even page buffers.

14. A multi-page copyback program method for a non-volatile memory device having a cell array including memory cells respectively coupled to word lines and bit lines, the method comprising:

precharging a plurality of odd bit lines of the bit lines to make the odd bit lines into shielding bit lines;

reading first data programmed into even memory cells coupled to a first word line of the word lines and storing the first data in a plurality of even page buffers respectively coupled to even bit lines of the bit lines via even sensing lines;

precharging the even bit lines to make the even bit lines into shielding bit lines;

reading second data programmed into odd memory cells coupled to the first word line and storing the second data in a plurality of odd page buffers respectively coupled to the odd bit line via odd sensing lines separated from the even sensing lines; and

copyback programming the first data stored in the plurality of even page buffers and the second data stored in the plurality of odd page buffers into even memory cells and odd memory cells coupled to a second word line of the word lines.

15. The multi-page read method as claimed in claim 14, wherein in order to make the odd bit line into the shielding bit lines, the odd sensing lines and the odd bit lines are precharged using the odd page buffers.

16. The multi-page read method as claimed in claim 14, wherein in order to make the even bit line into the shielding bit lines, the even sensing lines and the even bit lines are precharged using the even page buffers.