Physical layer and data link interface with adaptive speed

• US 7,257,079 B1
• Filed: 12/23/1999
• Issued: 08/14/2007
• Est. Priority Date: 12/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bachrach, Yuval
• Primary Examiner(s): Sheikh; Ayaz
• Assistant Examiner(s): LAFORGIA, CHRISTIAN A
• Application Number:
  US09/471,637
• Time in Patent Office: 2,791 Days
• Field of Search: 370/230, 370/230.1, 370/232, 370/233, 370/234, 370/419, 370/420, 370/311, 375/354, 709/227, 709/228, 709/229, 709/276, 709/236, 709/237, 709/238, 709/250, 709/232, 708/270, 708/271, 708/272, 708/273, 708/274, 708/275, 708/276, 708/277
• US Class Current: 370/230
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

A word-based interface between a MAC and a PHY, allowing for variable pin counts, variable PHY and MAC data speeds, and variable numbers of connected PHYs. The word-based interface allows for the PHY to provide PHY-to-MAC words to the MAC, and for the MAC to provided MAC-to-PHY words to the PHY, where the PHY-to-MAC words are synchronized with the MAC-to-PHY words. Data and commands are provided in fields of the words, and may be time multiplexed over the interface. Circuits within the MAC and PHY allow for the MAC to detect if a PHY is present, the number of active pins, and the number of PHYs connected. The reset and synchronization signals are integrated into a single reset/sync signal. Identification data is exchanged between the MAC and PHY so that the proper device driver for the PHY may be loaded independently of the BIOS.

Claims

1. A MAC comprising:

at least one PHY-to-MAC port to receive signals indicative of PHY-to-MAC words; and

at least one MAC-to-PHY port to transmit signals indicative of MAC-to-PHY words;

wherein the PHY-to-MAC words include slow mode PHY-to-MAC words, wherein a slow mode PHY-to-MAC word received by the MAC from a PHY includes a transmit cycle field to indicate whether the MAC is to provide data in a next MAC-to-PHY word transmitted by the MAC to the PHY subsequent to the MAC receiving the slow mode PHY-to-MAC word.

2. The MAC as set forth in claim 1, wherein the PHY-to-MAC words include equal speed mode PHY-to-MAC words, wherein an equal speed mode PHY-to-MAC word received by the MAC from the PHY indicates that the MAC is to provide data in the next MAC-to-PHY word.

3. The MAC as set forth in claim 1, wherein the PHY-to-MAC words and MAC-to-PHY words are each 12 bits wide.

4. The MAC as set forth in claim 1, wherein the transmit cycle field is in bit position nine, counting from zero, of a slow mode PHY-to-MAC word.

5. The MAC as set forth in claim 4, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven.

6. The MAC as set forth in claim 4, wherein

the PHY-to-MAC words include equal speed mode PHY-to-MAC words, wherein an equal speed mode PHY-to-MAC word received by the MAC from the PHY indicates that the MAC is to provide data in the next MAC-to-PHY word;

and

the PHY-to-MAC words and MAC-to-PHY words are each 12 bits wide.

7. The MAC as set forth in claim 6, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven;

and

the equal speed mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, a receive data valid field in bit position eleven, and a management frames protocol data out field in bit position nine.

8. A PHY to transmit and receive signals propagated on a medium, and to communicate with a MAC via PHY-to-MAC words and MAC-to-PHY words, the PHY comprising:

at least one MAC-to-PHY port to receive signals indicative of the MAC-to-PHY words; and

at least one PHY-to-MAC port to transmit signals indicative of the PHY-to-MAC words;

wherein the PHY-to-MAC words include slow mode PHY-to-MAC words, wherein a slow mode PHY-to-MAC word transmitted by the PHY and received by the MAC includes a transmit cycle field to indicate whether the MAC is requested by the PHY to provide data for transmission on the medium in a next MAC-to-PHY word transmitted by the MAC to the PHY subsequent to the MAC receiving the slow mode PHY-to-MAC word.

9. The PHY as set forth in claim 8, wherein the PHY-to-MAC words include equal speed mode PHY-to-MAC words, wherein an equal speed mode PHY-to-MAC word transmitted by the PHY to the MAC indicates that the MAC is to provide data in the next MAC-to-PHY word.

10. The PHY as set forth in claim 8, wherein the PHY-to-MAC words and MAC-to-PHY words are each 12 bits wide.

11. The PHY as set forth in claim 8, wherein the transmit cycle field is in bit position nine, counting from zero, of a slow mode PHY-to-MAC word.

12. The PHY as set forth in claim 11, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero;

one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven.

13. The PHY as set forth in claim 11, wherein

the PHY-to-MAC words include equal speed mode PHY-to-MAC words, wherein an equal speed mode PHY-to-MAC word transmitted by the PHY to the MAC indicates that the MAC is to provide data in the next MAC-to-PHY word;

and

the PHY-to-MAC words and MAC-to-PHY words are each 12 bits wide.

14. The PHY as set forth in claim 13, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven;

and

the equal speed mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, a receive data valid field in bit position eleven, and a management frames protocol data out field in bit position nine.

15. A computer system comprising:

a MAC; and

a PHY to receive and transmit signals propagated on a medium and connected to the MAC so that the MAC provides MAC-to-PHY words to the PHY and the PHY provides PHY-to-MAC words to the MAC;

wherein the PHY-to-MAC words and the MAC-to-PHY words are synchronously paired so that the MAC provides one MAC-to-PHY word to the PHY while the PHY provides one PHY-to-MAC word to the MAC;

wherein the PHY-to-MAC words include slow mode PHY-to-MAC words having a transmit cycle field;

wherein if the transmit cycle field of a first slow mode PHY-to-MAC word is set to a first value, the first slow mode PHY-to-MAC word being synchronously paired with a first MAC-to-PHY word, then the MAC is requested by the PHY to provide transmit data in a second MAC-to-PHY word for transmission over the medium, where the second MAC-to-PHY word succeeds the first MAC-to-PHY word, and if the transmit cycle field of the first slow mode PHY-to-MAC word is set to a second value different from the first value, then the MAC is requested by the PHY not to include transmit data in the second MAC-to-PHY word.

16. The computer system as set forth in claim 15, wherein the PHY-to-MAC words include equal speed mode PHY-to-MAC words.

17. The computer system as set forth in claim 15, wherein the PHY-to-MAC words and MAC-to-PHY words are 12 bits wide.

18. The computer system as set forth in claim 15, wherein the transmit cycle field is in bit position nine, counting from zero, of a slow mode PHY-to-MAC word.

19. The computer system as set forth in claim 18, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven.

20. The computer system as set forth in claim 18, wherein

the PHY-to-MAC words include equal speed mode PHY-to-MAC words;

and

the PHY-to-MAC words and MAC-to-PHY words are 12 bits wide.

21. The computer system as set forth in claim 20, wherein

the slow mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, and a receive data valid field in bit position eleven;

and

the equal speed mode PHY-to-MAC words have receive data fields in bit positions zero, one, two, four, five, six, seven, and eight, a carrier sense signal field in bit position three, a receive cycle field in bit position ten, a receive data valid field in bit position eleven, and a management frames protocol data out field in bit position nine.