Branch-aware FIFO for interprocessor data sharing

• US 7,257,665 B2
• Filed: 09/29/2003
• Issued: 08/14/2007
• Est. Priority Date: 09/29/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rosenbluth, Mark B., Niell, Jose S.
• Primary Examiner(s): Vincent; David
• Assistant Examiner(s): FERNANDEZ RIVAS, OMAR F
• Application Number:
  US10/674,835
• Publication Number:
  US 20050071602A1
• Time in Patent Office: 1,415 Days
• Field of Search: 706/10, 706/15, 711/1, 711/2, 711/5, 711/6, 711/100, 711/101, 711/109, 711/111, 711/114, 711/117, 711/132, 711/133, 711/140, 711/144, 711/203, 711/204, 711213-215, 710/1, 710/22, 710/24, 710/57, 712200-203, 712/14, 712/233, 712234-240
• US Class Current: 711/101
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Claims

1. A method, comprising:

storing one or more prior pop pointer values of a pop pointer;

prior to processing one or more pop requests,

storing data into a memory array of a FIFO memory, and

incrementing a push pointer;

processing one or more pop requests to read data from the FIFO memory;

reading a pop pointer value of the pop pointer and a push pointer value of the push pointer;

determining a status of the memory array in response to the pop pointer value, the push pointer value, a high threshold level, and a low threshold level, where the high threshold level is responsive to the lesser of a maximum branch resolution latency and the low threshold level;

receiving information to indicate at least one of the one or more pop requests was speculative and to indicate that a state of the pop pointer of the FIFO memory should be restored; and

restoring one of the one or more prior pop pointer values to the pop pointer in response to the information.

2. The method of claim 1, where,

the maximum branch resolution latency is a depth of an instruction pipeline in a processor, the processor to couple to the FIFO memory.

3. The method of claim 1, where,

the information includes a branch resolution latency, the branch latency being the number of instruction cycles to resolve a conditional branch instruction in a processor, the processor to couple to the FIFO memory.

4. An apparatus, comprising:

a first storage unit to store one or more prior pop pointer values of a pop pointer;

a FIFO memory;

a push pointer;

a pre-pop request logic that is to store data into a memory array of the FIFO memory and to increment the push pointer prior to processing one or more pop requests;

a pop-request logic to process one or more pop requests to read data from the FIFO memory, to read a pop pointer value of the pop pointer and a push pointer value of the push pointer, to determine a status of the memory array in response to the pop pointer value, the push pointer value, a high threshold level, and a low threshold level, where the high threshold level is responsive to the lesser of a maximum branch resolution latency and the low threshold level;

a receive logic to receive information to indicate at least one of the one or more pop requests was speculative and to indicate that a state of the pop pointer of the FIFO memory should be restored; and

a restore logic to restore one of the one or more prior pop pointer values to the pop pointer in response to the information.

5. The apparatus of claim 4, where,

the maximum branch resolution latency is a depth of an instruction pipeline in a processor, the processor to couple to the FIFO memory.

6. The apparatus of claim 4, where,

the information includes a branch resolution latency, the branch latency being the number of instruction cycles to resolve a conditional branch instruction in a processor, the processor to couple to the FIFO memory.