Sharing monitored cache lines across multiple cores

• US 7,257,679 B2
• Filed: 10/01/2004
• Issued: 08/14/2007
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Clark, Michael T.
• Primary Examiner(s): Portka; Gary
• Assistant Examiner(s): Ahmed; Hamdy S
• Application Number:
  US10/956,685
• Publication Number:
  US 20060075060A1
• Time in Patent Office: 1,047 Days
• Field of Search: 711/141
• US Class Current: 711/141
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

In one embodiment, a system comprises a first processor core and a second processor core. The first processor core is configured to communicate an address range indication identifying an address range that the first processor core is monitoring for an update. The first processor core is configured to communicate the address range indication responsive to executing a first instruction defined to cause the first processor core to monitor the address range. Coupled to receive the address range indication, the second processor core is configured, responsive to executing a store operation that updates at least one byte in the address range, to signal the first processing core. Coupled to receive the signal from the second processor core, the first processor core is configured to exit a first state in which the first processor core is awaiting the update in the address range responsive to the signal.

Claims

1. A system comprising:

a first processor core configured to communicate an address range indication identifying an address range that the first processor core is monitoring for an update, wherein the first processor core is configured to communicate the address range indication responsive to executing a first instruction defined to cause the first processor core to monitor the address range for update; and

a second processor core coupled to receive the address range indication and configured, responsive to executing a store operation that updates at least one byte in the address range, to signal the first processing core, and wherein the second processor core is configured to issue one or more coherency communications to coherently perform the store operation; and

wherein the first processor core is coupled to receive the signal from the second processor core prior to receiving the one or more coherency communications issued by the second processor core to coherently perform the store operation, and wherein the first processor core is configured to exit a first state in which the first processor core is awaiting the update in the address range, the first processor core configured to exit the first state responsive to the signal from the second processor core.

2. The system as recited in claim 1 wherein the address range indication comprises an address identifying a block of contiguous memory bytes.

3. The system as recited in claim 2 wherein the block contiguous memory bytes is a cache line.

4. The system as recited in claim 1 wherein the first processor core is coupled to an interface to communicate with other components of the computer system, and wherein the first processor core is further configured to exit the first state responsive to receiving an indication of update from the interface if the indication of update indicates an update in the address range.

5. The system as recited in claim 4 wherein the indication of update is a probe.

6. The system as recited in claim 1 wherein the first processor core comprises a first register configured to store the address range indication.

7. The system as recited in claim 6 wherein the second processor core comprises a second register configured to store a shadow copy of the address range indication.

8. The system as recited in claim 1 wherein the first state comprises a power conservation state.

25. The system as recited in claim 4 wherein the second processor core is coupled to signal the first processor core separate from the interface.

26. The system as recited in claim 8 wherein the first processor core is configured to enter the power conservation state responsive to executing a second instruction that indicates that the first processor core is to wait for the update in the address range.

9. A method comprising:

communicating, from a first processor core to a second processor core, an address range indication identifying an address range that the first processor core is monitoring for an update, wherein the communicating is responsive to executing a first instruction in the first processor core that is defined to cause the first processor core to monitor the address range for update;

executing a store operation that updates at least one byte in the address range in the second processor core;

issuing one or more coherency communications from the second processor core to coherently perform the store operation;

responsive to the store operation, signalling the first processor core; and

in the first processor core, exiting a first state, in which the first processor core is awaiting the update in the address range, wherein the exiting is responsive to the signalling and occurs prior to receiving the one or more coherency communications issued by the second processor core to coherently perform the store operation.

10. The method as recited in claim 9 wherein the address range indication comprises an address identifying a block of contiguous memory bytes.

11. The method as recited in claim 10 wherein the block contiguous memory bytes is a cache line.

12. The method as recited in claim 9 wherein the first processor core is coupled to an interface to communicate with other components of the computer system, the method further comprising exiting the first state in the first processor core responsive to receiving an indication of update from the interface if the indication of update indicates an update in the address range.

13. The method as recited in claim 12 wherein the indication of update is a probe.

14. The method as recited in claim 9 wherein the first state comprises a power conservation state.

15. A processor core comprising a monitor unit configured to monitor an address range for update responsive to a first instruction, wherein the processor core is configured to enter a first state to await the update to the address range, and wherein the monitor unit is configured to communicate an address range indication identifying the address range to a second processor core responsive to executing the first instruction, and wherein the monitor unit is configured to receive a signal from the second processor core indicating that the second processor core is updating at least one byte in the address range, and wherein the processor core is coupled to receive the signal prior to receiving one or more coherency communications issued by the second processor core to coherently perform the store operation, and wherein the processor core is configured to exit the first state responsive to the signal.

16. The processor core as recited in claim 15 wherein the address range indication comprises an address identifying a block of contiguous memory bytes.

17. The processor core as recited in claim 16 wherein the block contiguous memory bytes is a cache line.

18. The processor core as recited in claim 15 further having an interface to communicate with other components of the computer system, and wherein the processor core is further configured to exit the first state responsive to receiving an indication of update from the interface if the indication of update indicates an update in the address range.

19. The processor core as recited in claim 18 wherein the indication of update is a probe.

20. The processor core as recited in claim 15 wherein the monitor unit comprises a first register configured to store the address range indication.

21. The processor core as recited in claim 20 wherein the monitor unit further comprises a second register configured to store a shadow copy of a second address range indication received from the second processor core, wherein the second processor core is monitoring for an update in a second address range indicated by the second address range indication.

22. The processor core as recited in claim 21 wherein the monitor unit, responsive to the processor core executing a second store operation updating at least one byte in the second address range, is configured to signal the second processor core.

23. The processor core as recited in claim 15 wherein the first state comprises a power conservation state.

24. The processor core as recited in claim 23 wherein the processor core is configured to enter the first state responsive to executing a second instruction.

27. The processor core as recited in claim 18 wherein the processor core is coupled to receive the signal separate from the interface.