Method for integrally checking chip and package substrate layouts for errors

• US 7,257,784 B2
• Filed: 03/24/2005
• Issued: 08/14/2007
• Est. Priority Date: 03/24/2005
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Shih-Cheng, Cheng, Chia-Lin, Chen, Kuo-Yin, Wu, EJ
• Primary Examiner(s): Dinh; Paul
• Application Number:
  US11/089,108
• Publication Number:
  US 20060217916A1
• Time in Patent Office: 873 Days
• Field of Search: 716 3- 5, 716/11, 716/15
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.

Claims

1. A method for integrally checking a chip layout dataset and a package substrate layout dataset for errors, comprising:

converting the package substrate layout dataset from a first format into a second format in which the chip layout dataset is provided;

combining the chip layout dataset of the second format with the package substrate layout dataset of the second format into a combined dataset by using a predetermined modeling tool; and

checking the combined dataset for errors or design rule violations by providing a command file for instructing the modeling tool to run a layout versus schematic (LVS) check or a design rule check (DRC) on the combined dataset, wherein the command file includes an instruction of adding a predetermined value to each layer number of the package substrate layout dataset for avoiding double numbering among layers of the package substrate layout dataset and the chip layout dataset.

2. The method of claim 1, wherein the first format is a format used for multi-chip module (MCM) package layout.

3. The method of claim 1, wherein the second format is a graphic design system (GDS) II format.

4. The method of claim 1, wherein the converting further comprises:

providing a mapping file for identifying each layer of the package substrate layout dataset; and

adding the mapping file to the package substrate layout dataset.

5. The method of claim 4, further comprising adjusting coordinates of the package substrate layout dataset for matching coordinates of the chip layout dataset, before checking the combined dataset.

6. The method of claim 1, wherein the predetermined modeling tool is a Calibre modeling tool.

7. The method of claim 1, wherein the checking comprises providing the modeling tool with a text file having information with respect to connection locations of the package substrate layout dataset.

8. A system for integrally checking a chip layout dataset and a package substrate layout dataset for errors, comprising:

a first database storing the chip layout dataset in a first format;

a second database storing the package substrate layout dataset converted from a second format into the first format;

a modeling tool coupled to the first and second databases for combining the chip layout dataset and the package substrate layout dataset into a combined dataset, and checking the combined dataset for errors or design rule violations; and

a command file for instructing the modeling tool to add a predetermined value to each layer number of the package substrate layout dataset for avoiding double numbering among layers of the package substrate layout dataset and the chip layout dataset.

9. The system of claim 8, wherein the first format is a graphic design system (GDS) II format.

10. The system of claim 8, wherein the second format is a format used for multi-chip module (MCM) package layout.

11. The system of claim 8, wherein the package substrate layout dataset comprises a mapping file for identifying each layer of the package substrate layout dataset.

12. The system of claim 8, wherein the modeling tool is adapted for running a layout versus schematic (LVS) check or a design rule check (DRC) for the combined dataset.

13. The system of claim 8, further comprising a text file for providing the modeling tool with information regarding solder ball locations of the package substrate layout dataset.

14. A method for integrally checking a chip layout dataset and a package substrate layout dataset for errors, comprising:

providing a mapping file for identifying each layer of the package substrate layout dataset;

combining the mapping file into the package substrate layout dataset;

converting the package substrate layout dataset from a format used for multi-chip module (MCM) package layout into a graphic design system (GDS) II format in which the chip layout dataset is provided;

adjusting coordinates of the package substrate layout dataset for matching coordinates of the chip layout dataset;

combining the chip layout dataset of the GDS II format with the package substrate layout dataset of the GDS II format into a combined dataset by using a predetermined modeling tool; and

checking the combined dataset for errors or design rule violations by providing a command file for instructing the modeling tool to run a layout versus schematic (LVS) check or a design rule check (DRC) on the combined dataset, wherein the command file includes an instruction of adding a predetermined value to each layer number of the package substrate layout dataset for avoiding double numbering among layers of the package substrate layout dataset and the chip layout dataset.