Semiconductor device and method of making the same
First Claim
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1. A method of forming a semiconductor device, comprising:
- forming a gate on a semiconductor substrate;
forming a first spacer layer;
forming shallow lightly-doped regions on both sides of the gate in the substrate and being offset from the gate by the first spacer layer;
forming a second spacer layer having an etch rate comparable to an etch rate of the first spacer layer over the first spacer layer;
etching the first and second spacer layers to form a thick spacer;
forming source and drain regions on both sides of the gate in the substrate and being offset from the gate by the thick spacer; and
etching the thick spacer to form a thin spacer by etching the first and second spacer layers during the same etching step.
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Abstract
A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
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Citations
25 Claims
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1. A method of forming a semiconductor device, comprising:
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forming a gate on a semiconductor substrate; forming a first spacer layer; forming shallow lightly-doped regions on both sides of the gate in the substrate and being offset from the gate by the first spacer layer; forming a second spacer layer having an etch rate comparable to an etch rate of the first spacer layer over the first spacer layer; etching the first and second spacer layers to form a thick spacer; forming source and drain regions on both sides of the gate in the substrate and being offset from the gate by the thick spacer; and etching the thick spacer to form a thin spacer by etching the first and second spacer layers during the same etching step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of manufacturing a semiconductor device, comprising:
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forming a gate stack on a substrate by forming a dielectric layer on the substrate via chemical vapor deposition (CVD), forming a polysilicon layer on the dielectric layer, and patterning the dielectric and polysilicon layers via lithography to define the gate stack; forming a spacer liner layer over the gate stack and the substrate, the spacer liner layer comprising at least one of an oxide, a nitrided oxide, a nitride, a high-k material or a low-k material; forming lightly doped source and drain regions on opposing sides of the gate stack by implanting ions into the substrate through the spacer liner layer; forming via CVD a silicon nitride (SiN) spacer layer on the spacer liner layer, wherein the SiN spacer layer and the spacer liner layer have comparable etch rates; etching the SiN spacer layer and the spacer liner layer with a dry etch technique in the same etching step to form a thick spacer; forming source and drain regions by implanting an impurity into the substrate; etching the thick spacer to form a thin spacer; annealing the source and drain regions, the SiN spacer layer and the spacer liner layer; forming a silicide layer on the source region, the drain region and the gate stack; depositing a contact etch stop (CES) layer on the source region, the drain region and the gate stack; and forming source, drain and gate contacts contacting corresponding portions of the silicide layer over source, the drain and the gate stack. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of manufacturing a semiconductor device, comprising:
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forming a gate stack on a substrate; forming a first spacer layer on the gate stack, on sidewalls of the gate stack, and on the substrate on opposing sides of the gate, wherein the first spacer layer comprises an oxide and has a first etch rate; forming lightly doped regions in the substrate on opposing sides of the gate by implanting through portions of the first spacer layer formed on the substrate, and then forming a second spacer layer on the first spacer layer, wherein the second spacer layer comprises silicon nitride deposited by chemical vapor deposition (CVD) and has a high hydrofluoric etch rate comparable to the first etch rate of the first spacer layer; dry etching the first and second spacer layers to form a thick spacer; forming source and drain regions in the substrate on opposing sides of the gate by implanting around the thick spacer; etching the thick spacer to form a thin spacer by etching the first and second spacer layers in the same etch step using an etchant comprising hydrofluoric acid; forming a metal silicide on the source and drain regions of the substrate and on the gate stack; and depositing silicon nitride to form a contact etch stop layer.
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Specification