Glass-type planar substrate, use thereof, and method for the production thereof

• US 7,259,080 B2
• Filed: 08/22/2003
• Issued: 08/21/2007
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Merz, Peter, Quenzer, Hans-Joachim, Schulz, Arne-Veit
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US10/526,962
• Publication Number:
  US 20060110893A1
• Time in Patent Office: 1,460 Days
• Field of Search: 438/455, 438/456, 438/457, 438/459, 438/795, 438/107
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00611 Processes for the planarisation of structures planarising depositions C23C, H01L
• CPC Class Codes: B81C 2201/0126 Processes for the planarization of structures not provided for in B81C2201/0119 - B81C2201/0125
• CPC Class Codes: C03B 19/02 by casting molten glass, e.g. injection moulding
• CPC Class Codes: C03B 23/02 Re-forming glass sheets

Abstract

The invented method is distinguished by a combination of the following method steps:

• • provision of a semiconductor planar substrate composed of a semiconductor material,
  • reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness,
  • structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions,
  • joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness,
  • tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface region of reduced thickness forms a fluid-tight bond with the surface region of reduced thickness, with the planar substrate covering the impressions in a fluid-tight manner under vacuum conditions, and that in a second tempering phase, at least partial areas of the glasslike material flow into the impressions of the structured surface of the semiconductor planar substrate.

Claims

1. A method for structuring a planar substrate composed of a glasslike material,

characterized by a combination of the following method steps:

provision of a semiconductor planar substrate composed of a semiconductor material,

reduction of the thickness of said semiconductor planar substrate inside at least one surface region of said semiconductor planar substrate in order to form a raised surface region in relation to said surface planar region of reduced thickness,

structuring said raised surface region of said semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside said raised surface regions,

joining said structured surface of said semiconductor planar substrate with said glasslike planar substrate in such a manner that said glasslike planar substrate at least partially covers said surface planar region of reduced thickness,

tempering said joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, said glasslike planar substrate covering said surface region of reduced thickness forms a fluid-tight bond with said surface region of reduced thickness, with said planar substrate covering said impressions in a fluid-tight manner under vacuum conditions, and that in a second tempering phase, at least partial areas of the glasslike material flow into said impressions of said structured surface of said semiconductor planar substrate.

2. The method according to claim 1,

wherein said reduction in thickness is carried out at the edge region of said semiconductor planar substrate.

3. The method according to claim 2,

wherein said reduction in thickness is carried out in such a manner that said raised surface region is limited by a boundary area and is at least partially surrounded by said edge region of reduced thickness.

4. The method according to claim 2,

wherein said reduction in thickness is conducted by means of a wet-chemical etching process or a mechanical material processing method.

5. The method according to claim 1,

wherein said structuring of said raised surface region of said semiconductor planar substrate occurs by means of local mechanical removal of material in such a manner that impressions, which have a structural depth extending maximally to the plane of said surface region of reduced thickness, are worked inside said raised surface region by means of a removal tool.

6. The method according to claim 1,

wherein a sawing, abrading or milling tool is employed as said removal tool.

7. The method according to claim 5,

wherein said removal tool is moved in relation to said semiconductor planar substrate in such a manner that for selective removal of material, said removal tool is moved laterally over the surface of said surface region of reduced thickness in said raised surface region.

8. The method according to claim 1,

wherein said removal of material results in straight or curved running impressed channels within said raised surface region.

9. The method according to claim 8,

wherein said impressed channels are open toward the surface of said raised surface region and project open through the lateral boundary wall of said raised surface region.

10. The method according to claim 1,

wherein joining said semiconductor planar substrate with said structured planar substrate occurs by means of anodic bonding or thermal bonding.

11. The method according to claim 1,

wherein during said second tempering phase, normal pressure conditions or high pressure conditions prevail, which act on the surface of said glasslike planar substrate facing away from said semiconductor planar substrate.

12. The method according to claim 1,

wherein said tempering is carried out by controlling the temperature and the duration in such a manner that said glasslike material stops flowing into said impressions in said semiconductor planar substrate when said glasslike material completely fills said impressions.

13. The method according to claim 1,

wherein following said tempering, two-dimensional removal of material is carried out in such a manner that said glasslike planar substrate assumes a flush adjoining surface to said structured surface of said semiconductor planar substrate.

14. The method according to claim 1,

wherein semiconductor material is removed from the surface of said semiconductor planar substrate facing the surface joined with said glasslike planar substrate until at least partial areas of said glasslike material which flowed into said impressions are uncovered, said partial areas being flush with said surface of said semiconductor planar substrate.

15. The method according to claim 1,

wherein said semiconductor material is separated from said glasslike planar substrate.

16. The method according claim 15,

wherein said separation of said glasslike planar substrate from said semiconductor planar substrate occurs by means of etching away said semiconductor material.

17. The method according to claim 15,

wherein said separation of said two planar substrates occurs by providing a separation layer between said two planar substrates.

18. The method according to claim 17,

wherein said separation layer is applied onto said structured surface of said semiconductor planar substrate before joining said two planar substrates in a structure-retaining manner and is designed as a sacrificial layer which is destroyed by means of thermal and/or chemical action and permits separating said two substrates.

19. The method according to claim 17,

wherein a metal layer which has a melting point which lies below the melting points of said substrates is utilized as said separation layer.

20. The method according to claim 17,

wherein a layer capable of oxidizing which changes chemically under the addition of oxygen and/or thermal energy is utilized as said separation layer.

21. The method according to claim 17,

wherein a carbon layer, diamond layer, diamond-like layer or SIC is utilized as said separation layer.

22. The method according to claim 15,

wherein after separation of said two planar substrates from each other, said glasslike planar substrate is finished mechanically in order to retain said perforations penetrating perpendicularly through said planar substrate.

23. The method according to claim 22,

wherein said perforations are filled with an electrically conductive material.

24. The method according to claim 1,

wherein said glasslike material and said semiconductor material posses almost the same thermal expansion coefficients.

25. The method according to claim 1,

wherein said planar substrate composed of a glasslike material is a borosilicate glass.

26. The method according to claim 1,

wherein said semiconductor planar substrate is a silicon substrate.

27. The method according to claim 1,

wherein said structuring of said semiconductor planar substrate results in impressions of structural dimensions in the micrometer and/or sub-micrometer range.

28. The method according to claim 1,

wherein said impressions have an aspect ratio (height, respectively depth:

width) of 10;

1.

29. A glasslike planar substrate produced according to the method according to claim 1,

wherein said glasslike planar substrate is penetrated perpendicular to the substrate surface by perforations in which electrically conductive material is provided.

30. The glasslike planar substrate according to claim 29,

wherein said perforations filled with electrically conductive material are arranged arraylike.

31. Use of said glasslike planar substrate according to claim 29 for electrical contacting of components in microelectronics or micromechanics.

32. The use of said method according to claim 1 for producing a semiconductor planar substrate penetrated by a glasslike material.

33. A semiconductor planar substrate produced according to claim 32,

wherein said semiconductor planar substrate is a silicon wafer which, for the purpose of electrical and/or thermal insulation or for reasons of optical transparency, is provided with areas of glasslike material at least partly penetrating said silicon wafer.

34. The semiconductor planar substrate according to claim 32,

wherein said areas of glasslike material which at least partly penetrate said silicon wafer enclose at least one semiconductor region, and

wherein a metal layer is provided at least between said enclosed semiconductor region and said areas of glasslike material.

35. The semiconductor planar substrate according to claim 34,

wherein said enclosed semiconductor region is covered on both sides with an electrode structure respectively, each of which contacting said metal layer enclosing said semiconductor region.

36. A method for structuring a planar substrate composed of a glasslike material,

characterized by a combination of the following methods steps:

provision of a semiconductor planar substrate composed of a semiconductor material,

reduction of the thickness of said semiconductor planar substrate inside at least one surface region of said semiconductor planar substrate in order to form a raised surface region in relation to said surface region of reduced thickness,

structuring of said raised surface region of said semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside said raised surface region,

structurally conform deposition of a metal layer onto said structured, raised surface region,

joining said structured, metallized surface with said glasslike planar substrate in such a manner that said glasslike planar substrate at least partially covers said surface region of reduced thickness,

tempering said joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, said glasslike planar substrate covering said surface region of reduced thickness forms a fluid-tight bond with said surface region of reduced thickness, with said planar substrate covering said impressions under vacuum conditions in a fluid-tight manner, and that in a second tempering phase, at least partial areas of said glasslike material flow into said impressions of said structured, metallized surface of said semiconductor planar substrate.

37. The method according to claim 36,

wherein before structurally conform deposition of said metal layer on said structured raised surface region, a protective layer is deposited on said semiconductor planar substrate in order to prevent reactions between said semiconductor planar substrate and said metal layer.

38. The method according to claim 37, wherein thermal SiO₂ is deposited as said protective layer.

39. The method according to claim 36,

wherein before joining said structured, metallized surface with said glasslike planar substrate, at least partial areas of said metallized surface are removed.