High dynamic range image sensor

• US 7,259,413 B2
• Filed: 09/28/2004
• Issued: 08/21/2007
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Potter; Roy
• Application Number:
  US10/950,927
• Publication Number:
  US 20060071254A1
• Time in Patent Office: 1,057 Days
• Field of Search: 257/291, 257/292
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 31/035272 characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/621 for the control of blooming
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a leaking transistor and either a transfer gate or a reset gate. Alternatively, the HDR transistor may be a separate and individual transistor having the gate profile of a transfer gate or a reset gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor, adjusting the channel length of the transistor, or thinning the gate oxide on the transistor. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.

Claims

1. A pixel cell comprising:

a photosensor for producing photo-generated charges during an integration period comprising at least first and second segments; and

at least a first transistor coupled to said photosensor for draining charges away from said photosensor during one of said segments such that said photosensor has different charge integration characteristics in said first and second integration segments.

2. The pixel of claim 1 further comprising a second transistor coupled to said photosensor for draining charges away from said photosensor.

3. The pixel cell of claim 1, wherein the pixel is a CMOS imager pixel.

4. The pixel cell of claim 3, wherein the CMOS imager pixel is one of 3T, 4T, 5T, 6T, or 7T architectures.

5. The pixel cell of claim 1, wherein the photosensor is one of p-n and n-p photodiodes.

6. The pixel cell of claim 1, wherein the photosensor is a pinned photodiode having a first layer and a second layer.

7. The pixel cell of claim 6, wherein the pinned photodiode is a p-n-p or a n-p-n photodiode.

8. The pixel cell of claim 1, wherein the photosensor is a photogate.

9. The pixel cell of claim 1, wherein the photosensor is a photoconductor.

10. The pixel cell of claim 1, wherein said first transistor resets said photosensor.

11. The pixel cell of claim 1, wherein said first transistor also functions as a gate for transferring charges from said photosensor at the end of said integration period.

12. The pixel cell of claim 1, wherein said first integration segment has a first I-V slope.

13. The pixel cell of claim 12, wherein said first I-V slope is controlled by a first voltage applied to at least said first transistor.

14. The pixel cell of claim 12, wherein said second integration segment has a second I-V slope.

15. The pixel cell of claim 14, wherein said second I-V slope is controlled by a voltage applied to at least said first transistor.

16. The pixel cell of claim 15, wherein at least said first transistor has a voltage of greater than 0.0 V applied to it during said integration period.

17. The pixel cell of claim 1, wherein at least said first transistor is turned on after said integration period.

18. The pixel cell of claim 1, wherein at least said first transistor is turned on before said integration period.

19. The pixel cell of claim 1, wherein said first transistor is also a transfer gate for transferring charges from said photosensor to a storage node.

20. The pixel cell of claim 1, wherein said first transistor is also a reset gate for transferring charges from said photosensor to a voltage supply.

21. The pixel cell of claim 2, wherein said second transistor has a doping profile of a transfer transistor.

22. The pixel cell of claim 2, wherein said second transistor has a doping profile of a reset transistor.

23. The pixel cell of claim 1, further comprising a capacitor connected to a storage region of the pixel cell.