Programmable memory device, integrated circuit including the programmable memory device, and method of fabricating same

• US 7,259,419 B2
• Filed: 03/12/2004
• Issued: 08/21/2007
• Est. Priority Date: 05/26/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Hee-Seon, Koo, Jeoung-Mo
• Primary Examiner(s): Parker; Kenneth
• Assistant Examiner(s): DIAZ, JOSE R
• Application Number:
  US10/799,201
• Publication Number:
  US 20040238873A1
• Time in Patent Office: 1,257 Days
• Field of Search: 257314-321, 257/392, 257/638, 257/29.3, 438/201, 438/211, 438/257
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Claims

1. An integrated circuit, comprising:

a plurality of isolation layers for defining a first area, a second area, and a third area in a substrate;

a memory device including a floating gate formed over the first area and at least one isolation layer of the plurality of isolation layers, an inter-gate dielectric layer formed on the floating gate and including a composite layer having a silicon oxide layer and a silicon nitride layer, and a control gate formed on the inter-gate dielectric layer;

a first transistor including a first gate formed of the same material as the control gate, wherein the first gate is formed in the second area of the substrate on a first gate oxide layer having a thickness greater than or equal to a thickness of a tunnel oxide layer formed on the substrate, and a first source region and a first drain region formed in the second area at least one of under or adjacent both sides of the first gate; and

a second transistor including a second gate formed of the same material as the control gate, wherein the second gate is formed in the third area of the substrate on a second gate oxide layer thinner than the first gate oxide layer, and a second source region and a second drain region formed in the third area at least one of under or adjacent both sides of the second gate, wherein a first portion of the floating gate formed over the first area is narrower than a second portion of the floating gate formed over the at least one isolation layer, and wherein the control gate is formed over the second portion of the floating gate and not over the first portion of the floating gate, and a plurality of edges of the control gate do not extend to corresponding edges of the floating gate.

2. An integrated circuit, comprising:

a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer;

a first transistor including a first gate, a first gate oxide layer interposed between the first gate and the substrate, and a first source region and a first drain region formed in the active area at least one of under or adjacent both sides of the first gate; and

a second transistor including a second gate, a second gate oxide layer interposed between the second gate and the substrate, and a second source region and a second drain region formed in the active area at least one of under or adjacent both sides of the second gate, wherein the second gate oxide layer is thinner than the tunnel oxide layer, and the first gate oxide layer is thicker than the tunnel oxide layer and the second gate oxide layer.

3. The integrated circuit of claim 2, wherein the memory device further includes a source region and a drain region formed in the active area at least one of under or adjacent both sides of the floating gate.

4. The integrated circuit of claim 2, wherein the first gate and the second gate are formed of the same material as the control gate.