Multiple-gate device with floating back gate

• US 7,259,420 B2
• Filed: 07/28/2004
• Issued: 08/21/2007
• Est. Priority Date: 07/28/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A.
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): Nguyen; Dao H.
• Application Number:
  US10/710,680
• Publication Number:
  US 20060022253A1
• Time in Patent Office: 1,119 Days
• Field of Search: 257/315, 257/316
• US Class Current: 257/315
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

Claims

1. A multiple-gate transistor comprising:

a channel region;

a logic gate comprising a conductor adjacent a first side of said channel region;

a floating gate comprising a conductor adjacent a second side of said channel region, wherein said first side is opposite said second side such that said channel region is between said first side and said second side, and wherein said channel region is between said floating gate and said logic gate; and

a programming gate comprising a conductor adjacent said floating gate, wherein said floating gate is between said programming gate and said channel region,

wherein said logic gate performs a different function than said floating gate, wherein said logic gate performs a different function than said programming gate, and wherein said floating gate performs a different function than said programming gate.

2. The transistor in claim 1, further comprising a gate oxide between said channel region and said logic gate and a first insulator between said channel region and said floating gate, wherein said first insulator is thicker than said gate oxide.

3. The transistor in claim 1, wherein voltage in said logic gate causes said transistor to switch on and off.

4. The transistor in claim 1, wherein charge in said floating gate adjusts the threshold voltage of said transistor.

5. The transistor in claim 1, wherein said transistor comprises a fin-type field effect transistor (FinFET).

6. The transistor in claim 1, further comprising source and drain regions at ends of said channel region, wherein said channel region comprises the middle portion of a fin structure and said source and drain regions comprise end portions of said fin structure.

7. The transistor in claim 1, wherein said floating gate is electrically insulated from other structures.

8. A multiple-gate transistor comprising:

a channel region;

source and drain regions at ends of said channel region;

a gate oxide on a first side of said channel region;

a logic gate comprising a conductor adjacent said first gate oxide, wherein said gate oxide is between said logic gate and said channel region, and wherein voltage in said logic gate causes said transistor to switch on and off;

a first insulator on a second side of said channel region, wherein said second side of said channel region is opposite said first side such that said channel region is between said first side and said second side;

a floating gate comprising a conductor adjacent said first insulator, wherein said first insulator is between said floating gate and said channel region, wherein said channel region is between said floating gate and said logic gate, and wherein charge in said floating gate adjusts the threshold voltage of said transistor;

a second insulator adjacent said floating gate; and

a programming gate comprising a conductor adjacent said second insulator, wherein said second insulator is between said programming gate and said floating gate, wherein a voltage change of said programming gate changes a voltage of said floating gate,

wherein said logic gate performs a different function than said floating gate, wherein said logic gate performs a different function than said programming gate, and wherein said floating gate performs a different function than said programming gate.

9. The transistor in claim 8, wherein said first insulator is thicker than said gate oxide.

10. The transistor in claim 8, wherein said transistor comprises a fin-type field effect transistor (FinFET).

11. The transistor in claim 8, wherein said channel region comprises the middle portion of a fin structure and said source and drain regions comprise end portions of said fin structure.

12. The transistor in claim 8, wherein said floating gate is electrically insulated from other structures.

13. A multiple-gate transistor comprising:

a channel region;

a logic gate comprising a conductor adjacent a first side of said channel region, wherein voltage in said logic gate causes said transistor to switch on and off;

a floating gate comprising a conductor adjacent a second side of said channel region, wherein said first side is opposite said second side such that said channel region is between said first side and said second side, wherein said channel region is between said floating gate and said logic gate, and wherein charge in said floating gate adjusts the threshold voltage of said transistor; and

a programming gate comprising a conductor adjacent said floating gate, wherein said floating gate is between said programming gate and said channel region.

14. The transistor in claim 13, further comprising a gate oxide between said channel region and said logic gate and a first insulator between said channel region and said floating gate, wherein said first insulator is thicker than said gate oxide.

15. The transistor in claim 13, wherein said transistor comprises a fin-type field effect transistor (FinFET).

16. The transistor in claim 13, further comprising source and drain regions at ends of said channel region, wherein said channel region comprises the middle portion of a fin structure and said source and drain regions comprise end portions of said fin structure.

17. The transistor in claim 13, wherein said floating gate is electrically insulated from other structures.

18. A multiple-gate transistor comprising:

a channel region;

a logic gate comprising a conductor adjacent a first side of said channel region, wherein voltage in said logic gate causes said transistor to switch on and off, and wherein said transistor comprises a fin-type field effect transistor (FinFET);

a floating gate comprising a conductor adjacent a second side of said channel region, wherein said first side is opposite said second side such that said channel region is between said first side and said second side, wherein said channel region is between said floating gate and said logic gate, and wherein charge in said floating gate adjusts the threshold voltage of said transistor; and

a programming gate comprising a conductor adjacent said floating gate, wherein said floating gate is between said programming gate and said channel region.

19. The transistor in claim 18, further comprising a gate oxide between said channel region and said logic gate and a first insulator between said channel region and said floating gate, wherein said first insulator is thicker than said gate oxide.

20. The transistor in claim 18, further comprising source and drain regions at ends of said channel region, wherein said channel region comprises the middle portion of a fin structure and said source and drain regions comprise end portions of said fin structure.

21. The transistor in claim 18, wherein said floating gate is electrically insulated from other structures.