System and method to use dynamic feedback of analog to digital converter sample rate to adaptively lock the sample rate to input frequency
First Claim
1. A system for measuring power, comprising:
- an analog to digital (ADC) converter for sampling an analog input line signal;
a measuring module coupled to said ADC converter for measuring a predetermined number of line cycles of said analog input line signal;
an ADC cycle counter coupled to said ADC converter for measuring an actual sample count by said ADC converter of said analog input line signal over said predetermined number of line cycles; and
a calculation block coupled to said ADC cycle counter and said measuring module for determining an error rate between said actual sample count and an ideal sample count of said analog input line signal over said predetermined number of line cycles, wherein said ideal sample count is based on a predetermined over sample rate.
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Abstract
A system and method for dynamically lock the sample rate of an analog to digital (ADC) converter to an input frequency. Specifically, a system for measuring power is disclosed. The system includes an ADC converter, a measuring module, an ADC cycle counter, and a calculation block coupled together. The ADC converter samples an analog input line signal. The measuring module measures a predetermined number of line cycles of the analog input line signal. The ADC cycle counter measures an actual sample count of the analog input line signal by the ADC converter over the predetermined number of line cycles. The calculation block determines an error rate between the actual sample count and an ideal sample count that is based on a predetermined over sample rate.
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Citations
21 Claims
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1. A system for measuring power, comprising:
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an analog to digital (ADC) converter for sampling an analog input line signal; a measuring module coupled to said ADC converter for measuring a predetermined number of line cycles of said analog input line signal; an ADC cycle counter coupled to said ADC converter for measuring an actual sample count by said ADC converter of said analog input line signal over said predetermined number of line cycles; and a calculation block coupled to said ADC cycle counter and said measuring module for determining an error rate between said actual sample count and an ideal sample count of said analog input line signal over said predetermined number of line cycles, wherein said ideal sample count is based on a predetermined over sample rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for measuring line frequency, comprising:
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an analog to digital (ADC) converter for sampling an analog input line signal; a timer for measuring a time period; an ADC cycle counter coupled to said ADC converter for counting a number of ADC cycles of said analog input line signal over said time period; a calculation block coupled to said timer and said ADC cycle counter for determining a line frequency of said analog input line signal by dividing said number of ADC cycles by said time period and by dividing said number of ADC cycles by a predetermined over sample rate. - View Dependent Claims (10, 11, 12)
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13. A method for measuring power, comprising:
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measuring a predetermined number of line cycles of an analog input line signal; calculating an ideal sample count by an analog to digital converter (ADC) of said analog input line signal over said predetermined number of line cycles, wherein said ideal sample count is based on a predetermined over sample rate; measuring an actual sample count by said ADC of said analog input line signal of said analog input line signal over said predetermined number of line cycles; determining an error rate between said actual sample count and said ideal sample count; and driving said actual sample count to said ideal sample count by adjusting overall sample timing of said ADC by a factor proportional to said error rate. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification