Method and system for ESD protection of balanced circuit board lines

• US 7,259,949 B2
• Filed: 09/29/2004
• Issued: 08/21/2007
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Shintani, Peter, Tahara, Yoshihisa
• Primary Examiner(s): Jackson; Stephen W.
• Assistant Examiner(s): PATEL, DHARTI HARIDAS
• Application Number:
  US10/953,840
• Publication Number:
  US 20060067023A1
• Time in Patent Office: 1,056 Days
• Field of Search: 361/91.1, 361/56, 361/111
• US Class Current: 361/91.1
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H05K 1/0259 Electrostatic discharge [ESD] protection
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09236 Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672

Abstract

An array of electrostatic discharge (ESD) devices conforms to the pitch defined by balanced signal lines on a printed wiring board (PWB) so that the array does not unduly affect the design impedance of the balanced lines.

Claims

1. A printed wiring board (PWB), comprising:

at least one pair of balanced signal lines defining a pitch; and

at least one array of electrostatic discharge (ESD) devices electrically connecting each of the balanced signal lines to ground, the array conforming to the pitch, wherein the lateral distance between at least one of;

successive ESD devices in the array, or successive ESD device traces, equals the pitch.

2. The PWB of claim 1, wherein the pair of balanced signal lines includes first and second lines and the array includes first and second ESD devices respectively connected to the first and second lines, a ground being defined by the PWB, the first and second ESD devices being disposed on opposite sides of the ground from each other.

3. The PWB of claim 1, comprising two pair of balanced signal lines carrying at least one of:

universal serial bus (USB) signals, or signals conforming to IEEE-1394 standard.

4. The PWB of claim 1, comprising three pair of balanced signal lines carrying signals conforming to IEEE-1394 standards and associated power line signals.

5. The PWB of claim 1, comprising four pair of balanced signal lines carrying at least one of:

Digital Visual interface (DVI) signals, or High Definition Multimedia Interface (HDMI) signals.

6. The PWB of claim 1, comprising four pair of balanced signal lines carrying DVI or HDMI signals and two lines carrying associated display data channel (DDC) signals.

7. The PWB of claim 1, comprising at least one connector on the PWB and defining the pitch.

8. The PWB of claim 1, wherein the array includes one and only one connection to ground established by at least one of:

a lead on an end of the array, or a grounding pad on a surface of the array.

9. An electrostatic discharge (ESD) device apparatus for a printed wiring board (PWB) having at least one pair of balanced signal lines, comprising:

plural ESD devices, one for each line in a pair of related balanced signal lines sought to be protected; and

plural traces, each trace respectively connected an ESD device, the balanced signal lines defining a pitch and the traces defining a pitch substantially equal to the pitch defined by the balanced signal lines.

10. The ESD device apparatus of claim 9, wherein the balanced signal lines are associated with a design impedance, and at least the width of each trace is established such that the PWB with ESD device apparatus conforms to the design impedance.

11. The ESD device apparatus of claim 9, wherein the balanced signal lines are associated with a design impedance, and at least the cross-sectional area of each trace is established such that the PWB with ESD device apparatus conforms to the design impedance.

12. The ESD device apparatus of claim 9, wherein the pair of balanced signal lines includes first and second lines and the apparatus includes first and second ESD devices respectively connected to the first and second lines, a ground being defined by the PWB, the first and second ESD devices being disposed on opposite sides of the ground from each other.

13. The ESD device apparatus of claim 9, comprising two pair of balanced signal lines carrying at least one of:

universal serial bus (USB) signals, or signals conforming to IEEE-1394 standard.

14. The ESD device apparatus of claim 9, comprising three pair of balanced signal lines carrying signals conforming to IEEE-1394 standard and associated power line signals.

15. The ESD device apparatus of claim 9, comprising four pair of balanced signal lines carrying at least one of:

Digital Visual Interface (DVI) signals, or High Definition Multimedia Interface (HDMI) signals.

16. The ESD device apparatus of claim 9, comprising four pair of balanced signal lines carrying DVI or HDMI signals and two lines carrying associated display data channel (DDC) signals.

17. The ESD device apparatus of claim 9, wherein the apparatus includes one and only one connection to ground established by at least one of:

a lead on an end of an array of ESD devices, or a grounding pad on a surface of an array of ESD devices.