Program control circuit of flash memory device having MLC and method thereof

• US 7,259,976 B2
• Filed: 12/21/2005
• Issued: 08/21/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Chang, Hee Hyun, Lee, Hee Youl
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/275,281
• Publication Number:
  US 20070002629A1
• Time in Patent Office: 608 Days
• Field of Search: 365/185.03, 365/185.19, 365/185.11
• US Class Current: 365/3
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Claims

1. A program control method of a flash memory device including a plurality of MLCs that shares word lines and bit lines, comprising:

a first program to affect programming of MLCs of a selected page by applying a program voltage, which is increased by a step voltage, to a selected word line of the word lines during a first predetermined time in each of first to Ith (I is an integer) program cycles in response to a first cycle control signal;

a second program to affect programming of the MLCs of the selected page by applying a first last program voltage (i.e., a program voltage that has been finally increased in the first program step) to the selected word line, while increasing the last program voltage by a step voltage, during a second predetermined time in each of first to (I+1)th to Jth (J is an integer) program cycles in response to a second cycle control signal; and

a third program to affect programming of the MLCs of the selected page by applying a second last program voltage (i.e., a program voltage that has been finally increased in the second program step) to the selected word line, while increasing the second to last program voltage by the step voltage, during a third predetermined time in each of first to (J+1)th to Kth (K is an integer) program cycles in response to a third cycle control signal.

2. The program control method as claimed in claim 1, wherein the third predetermined time is longer than the second predetermined time, and the second predetermined time is longer than the first predetermined time.

3. The program control method as claimed in claim 2, wherein the first program includes:

programming the MLCs of the selected page by applying the program voltage to the selected word line during the first predetermined time;

verifying the MLCs of the selected page by applying a verify voltage to the selected word line during a fourth predetermined time;

determining whether a program cycle number is I;

if it is determined that the program cycle number is not the I, increasing the program voltage as much as the step voltage and then repeatedly performing the program step to determination step; and

if it is determined that the program cycle number is I, stopping the first program step.

4. The program control method as claimed in claim 3, wherein the step of programming the MLCs includes the steps of:

allowing a controller to generate the first cycle control signal;

allowing a clock signal generator to generate a clock signal and an inverted clock signal in response to the first cycle control signal; and

allowing a voltage select circuit to apply the program voltage to the X-decoder during the first predetermined time in response to the clock signal, enabling the X-decoder to supply the program voltage to the selected word line.

5. The program control method as claimed in claim 3, wherein verifying the MLCs includes:

allowing a verify data comparator to compare verify data corresponding to read data of the MLCs of the selected page with reference data and to output compare signals;

allowing a controller to output bit line masking signals in response to the compare signals; and

allowing a page buffer circuit connected to the bit lines to apply a bit line bias voltage for prohibiting program bit line(s) connected to MLCs on which the first program step has been completed of the MLCs, in response to the bit line masking signals.

6. The program control method as claimed in claim 2, wherein the second program includes the steps of:

increasing the first last program voltage as much as the step voltage;

programming the MLCs of the selected page by supplying the increased program voltage to the selected word line during the second predetermined time;

verifying the MLCs of the selected page by supplying a first or second verify voltage to the selected word line during a fourth predetermined time;

determining whether a program cycle number is J;

if it is determined that the program cycle number is not J, increasing the increased program voltage as much as the step voltage and then repeatedly performing the program step to determination step; and

if it is determined that the program cycle number is J, stopping the second program step.

7. The program control method as claimed in claim 6, wherein programming the MLCs includes:

allowing a controller to generate the second cycle control signal;

allowing a clock signal generator to generate a clock signal and an inverted clock signal in response to the second cycle control signal; and

allowing a voltage select circuit to apply the increased program voltage to the X-decoder during the second predetermined time in response to the clock signal, enabling the X-decoder to supply the increased program voltage to the selected word line.

8. The program control method as claimed in claim 6, wherein verifying the MLCs includes:

allowing a verify data comparator to compare verify data corresponding to read data of the MLCs of the selected page with reference data and to output compare signals;

allowing a controller to output bit line masking signals in response to the compare signals; and

allowing a page buffer circuit connected to the bit lines to apply a bit line bias voltage for prohibiting program bit line(s) connected to MLCs on which the second program step has been completed, of the MLCs, in response to the bit line masking signals.

9. The program control method as claimed in claim 2, wherein the third program includes:

increasing the second last program voltage as much as the step voltage;

programming the MLCs of the selected page by supplying the increased program voltage to the selected word line during the third predetermined time;

verifying the MLCs of the selected page by supplying a verify voltage to the selected word line during a fourth predetermined time;

determining whether a program cycle number is K;

if it is determined that the program cycle number is not K, increasing the increased program voltage as much as the step voltage and then repeatedly performing the program step to determination step; and

if it is determined that the program cycle number is K, stopping the third program step.

10. The program control method as claimed in claim 9, wherein programming the MLCs includes:

allowing a controller to generate the third cycle control signal;

allowing a clock signal generator to generate a clock signal and an inverted clock signal in response to the third cycle control signal; and

allowing a voltage select circuit to apply the increased program voltage to the X-decoder during the third predetermined time in response to the clock signal, enabling the X-decoder to supply the increased program voltage to the selected word line.

11. The program control method as claimed in claim 9, wherein verifying the MLCs includes:

allowing a verify data comparator to compare verify data corresponding to read data of the MLCs of the selected page with reference data and to output compare signals;

allowing a controller to output bit line masking signals in response to the compare signals; and

allowing a page buffer circuit connected to the bit lines to apply a bit line bias voltage for prohibiting program bit line(s) connected to MLCs on which the third program step has been completed, of the MLCs, in response to the bit line masking signals.