Systems for variable programming of non-volatile memory

• US 7,259,987 B2
• Filed: 12/21/2005
• Issued: 08/21/2007
• Est. Priority Date: 04/06/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Wang, Chi-Ming
• Primary Examiner(s): Nguyen; Van Thu
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US11/316,141
• Publication Number:
  US 20060133138A1
• Time in Patent Office: 608 Days
• Field of Search: 365/185.03, 365/185.14, 365/185.33, 365/185.18, 365/185.24, 365/185.22
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Claims

1. A non-volatile memory system, comprising:

a set of non-volatile storage elements, said set of non-volatile storage elements includes a first subset of non-volatile storage elements having a first set of physical states and a second subset of non-volatile storage elements having said first set of physical states, one or more of said first set of physical states are at lower voltages for said second subset of non-volatile storage elements than for said first subset of non-volatile storage elements; and

managing circuitry in communication with said non-volatile storage elements, said managing circuitry reads said set by;

reading said first subset, said step of reading includes applying one or more first read values to determine if said one or more storage elements of said first subset are programmed to said first physical state, and

reading said second subset, said step of reading includes applying one or more second read values to determine if said one or more storage elements of said second subset are programmed to said second physical state;

wherein said one or more second read values are less than said one or more first read values.