Semiconductor memory device with a memory cell array formed on a semiconductor substrate

• US 7,259,992 B2
• Filed: 05/25/2005
• Issued: 08/21/2007
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shirota, Riichiro
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): King; Douglas
• Application Number:
  US11/136,369
• Publication Number:
  US 20050265079A1
• Time in Patent Office: 818 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.27, 365/185.21, 365/203
• US Class Current: 365/185.21
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory cell array on a region of a substrate, the cell array having word lines, bit lines and memory cells at crossings between the word and bit lines, drain and source of each memory cell coupled to a bit line and source line, respectively; and a sense amplifier circuit reading data of selected memory cells. The device has a data read mode detecting whether cell current flows from a bit line to the source line in accordance with data of a memory cell under the condition the well region is set at a base potential; a selected word line is applied with a read voltage, which turns on or off the memory cell in accordance with data thereof; the source line is applied with a first voltage higher than the base potential; and the selected bit line is applied with a second voltage higher than the first voltage.

Claims

1. A semiconductor memory device comprising:

a memory cell array formed on a well region of a semiconductor substrate, said memory cell array having word lines, bit lines crossing the word lines, and electrically rewritable and non-volatile memory cells disposed at the crossings between the word lines and bit lines, drain and source of each memory cell being coupled to a bit line and a source line, respectively; and

a sense amplifier circuit connected to the bit lines for reading data of selected memory cells, wherein

said device has such a data read mode as to detect whether cell current flows or not from a selected bit line to the source line in accordance with data of a selected memory cell under the condition of;

the well region is set at a base potential;

a selected word line is applied with a read voltage, which turns on or off the selected memory cell in accordance with data thereof;

the source line is applied with a first positive voltage higher than the base potential; and

the selected bit line is applied with a second positive voltage higher than the first positive voltage, wherein

said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, wherein

in the data read mode, non-selected word lines in a NAND cell unit including the selected memory cell are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data; and

a non-selected bit line disposed adjacent to the selected bit line is applied with the first positive voltage, and wherein

in the data read mode, in case the selected memory cell in the NAND cell unit is positioned in a certain region near the bit line, the source line is set at ground potential, while in case the selected memory cell is positioned outside of the certain region, the first positive voltage applied to the source line is changed to be higher as the position of the selected memory cell becomes nearer to the source line.

2. The semiconductor memory device according to claim 1, wherein

said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, and wherein

the device has such a data write mode as to repeat a write voltage application operation for applying a write voltage to a selected word line, thereby writing data in selected memory cells along the selected word line, and a verify-read operation for verifying the write states of the selected memory cells, and wherein

in the verify-read operation in the data write mode, the well region is applied with a base potential;

the selected word line is applied with a verify-read voltage, which turns on or off the selected memory cells in accordance with data thereof;

non-selected word lines in the NAND cell unit including the selected word line are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data;

the source line is applied with a positive voltage higher than the base potential; and

a selected bit line is applied with a second positive voltage higher than the first positive voltage.

3. The semiconductor memory device according to claim 1, wherein

each memory cell has a stacked gate transistor structure with a gate length of 100 nm or less.

4. A semiconductor memory device comprising a memory cell array formed on a well region of a semiconductor substrate, each memory cell within said memory cell array storing one of two or more threshold voltage distributions as data in a non-volatile manner, wherein

said device has such a data read mode as to detect whether cell current flows or not in a selected memory cell on condition that a reverse bias voltage is applied between source of the selected memory cell and the well region for lessening an inhibited range between the threshold voltage distributions, wherein

said memory cell array having word lines, bit lines crossing the word lines, and electrically rewritable and non-volatile memory cells disposed at the crossings between the word lines and bit lines, drain and source of each memory cell being coupled to the bit line and a source line, respectively, wherein

the data read mode is performed by detecting whether cell current flows or not from a selected bit line to the source line in accordance with data of a selected memory cell under the condition of:

the well region is set at a base potential;

a selected word line is applied with a read voltage, which turns on or off the selected memory cell in accordance with data thereof;

the source line is applied with a first positive voltage higher than the base potential; and

the selected bit line is applied with a second positive voltage higher than the first positive voltage, wherein

said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, wherein

in the data read mode, non-selected word lines in a NAND cell unit including the selected memory cell are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data; and

a non-selected bit line disposed adjacent to the selected bit line is applied with the first positive voltage, and wherein

in the data read mode, in case the selected memory cell in the NAND cell unit is positioned in a certain region near the bit line, the source line is set at ground potential, while in case the selected memory cell is positioned outside of the certain region, the first positive voltage applied to the source line is changed to be higher as the position of the selected memory cell becomes nearer to the source line.

5. The semiconductor memory device according to claim 4, further comprising:

a sense amplifier circuit connected to the bit lines for reading data of selected memory cells, wherein

after having precharged the selected bit line to the second positive voltage, the sense amplifier circuit detects whether the selected bit line is discharged or not via the selected memory cell in the data read mode.

6. The semiconductor memory device according to claim 4, wherein

said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, and wherein

the device has such a data write mode as to repeat a write voltage application operation for applying a write voltage to the selected word line, thereby writing data in selected memory cells along the selected word line, and a verify-read operation for verifying the write state of the selected memory cells, and wherein

the verify-read operation in the data write mode is performed under the condition of:

the well region is applied with a base potential;

the selected word line is applied with a verify-read voltage, which turns on or off the selected memory cells in accordance with data thereof;

non-selected word lines in the NAND cell unit including the selected word line are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data;

the source line is applied with a positive voltage higher than the base potential; and

a selected bit line is applied with a second positive voltage higher than the first positive voltage.

7. The semiconductor memory device according to claim 4, wherein

each memory cell has a stacked gate transistor structure with a gate length of 100 nm or less.

8. A semiconductor memory device comprising:

a device base including a semiconductor substrate and a semiconductor layer formed with an insulator film interposed therebetween;

a memory cell array having electrically rewritable and non-volatile memory cells formed on the semiconductor layer of the device base; and

a sense amplifier circuit coupled to a bit line of the memory cell array for detecting whether cell current flows or not from the bit line to a source line via a selected memory cell, thereby reading out data, wherein

at a data read time, the source line is applied with a first positive voltage; and

the bit line is applied with a second positive voltage higher than the first positive voltage, wherein

said memory cell array is formed of NAND cell units so arranged as to share a source line, each NAND cell unit having memory cells arranged in the direction of the bit line and connected in series, control gates of which are coupled to different word lines, respectively, a first select gate transistor for coupling one end of the NAND cell unit to a bit line, and a second select gate transistor for coupling the other end to the source line, wherein

in the data read mode, non-selected word lines in a NAND cell unit including the selected memory cell are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data; and

a non-selected bit line disposed adjacent to the selected bit line is applied with the first positive voltage, and wherein

in the data read mode, in case the selected memory cell in the NAND cell unit is positioned in a certain region near the bit line, the source line is set at ground potential, while in case the selected memory cell is positioned outside of the certain region, the first positive voltage applied to the source line is changed to be higher as the position of the selected memory cell becomes nearer to the source line.

9. The semiconductor memory device according to claim 8, wherein

each NAND cell unit has plural memory cells connected in series and select gate transistors for coupling both ends thereof to a bit line and a source line, respectively.

10. The semiconductor memory device according to claim 8, wherein

the device has such a data write mode as to repeat a write voltage application operation for applying a write voltage to a selected word line, thereby writing data in selected memory cells along the selected word line, and a verify-read operation for verifying the write states of the selected memory cells, and wherein

in the verify-read operation in the data write mode, the well region is applied with a base potential;

the selected word line is applied with a verify-read voltage, which turns on or off the selected memory cells in accordance with data thereof non-selected word lines in the NAND cell unit including the selected word line are applied with a pass voltage, which turns on memory cells without regard to cells'"'"' data;

the source line is applied with a positive voltage higher than the base potential; and

a selected bit line is applied with a second positive voltage higher than the first positive voltage.

11. The semiconductor memory device according to claim 8, wherein

each memory cell has a stacked gate transistor structure with a gate length of 100 nm or less.