Method and apparatus for managing energy usage of processors while executing protocol state machines

• US 7,260,106 B2
• Filed: 01/24/2002
• Issued: 08/21/2007
• Est. Priority Date: 01/24/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Lakshman, Yavatkar, Rajendra
• Primary Examiner(s): NGUYEN, STEVEN H D
• Application Number:
  US10/056,160
• Publication Number:
  US 20030137945A1
• Time in Patent Office: 2,035 Days
• Field of Search: None
• US Class Current: 370/428
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus of implementing protocol state machines that conserve energy on energy conscious devices is disclosed. Under this method, most of the energy consuming protocol state machine context invocations or operations are aggregated in time and are scheduled at regular intervals. Such an aggregation leads to many contexts executing concurrently in a burst prior to entering a dormant state. Thus, resource usage can reach a predictable rate pattern of idle and active cycles. With such a pattern, it is possible to take advantage of the energy saving features of processors by downshifting the processor clock speed and use of other resources such as peripherals and buses. The intervals are configured to achieve a tradeoff between timely execution and energy consumption. The aggregation operates across two dimensions, namely, multiple instances of a protocol state machine and multiple layers of protocols in a layered architecture.

Claims

1. A system to manage energy usage of a processor, comprising:

a data communication network;

a transmitter, coupled to the data communication network, to invoke a protocol state machine to send a packet and to wait for an acknowledgment of receipt;

a receiver, in communication with the transmitter coupled to the data communication network, to receive, process, and verify the packet and to send the acknowledgment of receipt of the packet;

an incoming packet buffer, coupled to the protocol state machine in the transmitter, to store an incoming packet to be transmitted by the transmitter; and

a processor, coupled to the protocol state machine in the transmitter, the processor enters a low power, low clock rate mode while waiting for the acknowledgment of receipt of the packet from the receiver,

wherein the protocol state machine manages a power level of the processor based on a utilized capacity of the buffer and the transmitter awakens when the incoming packet buffer reaches a low water mark.

2. The system of claim 1, wherein the data communication network includes at least one of the Internet and an Intranet.

3. The system of claim 1, wherein the processor in the transmitter begins in a high power, high clock rate mode.

4. The system of claim 1, wherein the transmitter performs tasks to create packets for transmission, the tasks including at least one of dividing data into packets, adding protocol headers, or computing checksums.

5. The system of claim 1, wherein the receiver includes an application buffer and after the receiver receives the packet, the packet is stored in the application buffer.

6. The system of claim 5, wherein the receiver includes a receiver protocol state machine and a receiver processor, and the receiver protocol state machine manages a power level of the receiver processor based on a utilized capacity of the application buffer.

7. The system of claim 6, wherein the receiver processor begins in a low power, low clock rate mode.

8. The system of claim 6, wherein the receiver processor enters a high power, high clock rate mode when the application buffer reaches a maximum capacity.

9. An article comprising:

a computer-readable storage medium having stored thereon instructions that when executed by a computer result in the following;

receiving a data packet at a receiver protocol state machine, the data packet being transmitted from a transmitter protocol state machine over a data communication network;

depositing the data packet in an application buffer;

processing and verifying the data packet; and

transmitting an acknowledgment of receipt of the data packet to the transmitter protocol state machine, wherein the receiver protocol state machine manages a power level of a processor in the receiver which is coupled to the receiver protocol state machine based on a utilized capacity of the application buffer, the processor in the receiver switching to a high-power, high clock rate mode from a lower power, low clock rate mode when the application buffer reaches a threshold.

10. The article of claim 9, wherein the utilized capacity of the application buffer and a timer cause periodic patterns in data packet reception, which are used to manage power and frequency of a processor in a transmitting device.

11. The article of claim 9, wherein the data communication network includes at least one of the Internet and an Intranet.

12. An article comprising:

a computer-readable storage medium having stored thereon instructions that when executed by a computer result in the following;

receiving a data packet at a receiver protocol state machine, the data packet being transmitted from a transmitter protocol state machine over a data communication network;

depositing the data packet in an application buffer;

processing and verifying the data packet; and

transmitting an acknowledgment of receipt of the data packet to the transmitter protocol state machine, wherein the receiver protocol state machine manages a power level of a processor coupled to the receiver protocol state machine based on a utilized capacity of the application buffer, and a processor in the receiver enters a high power, high clock rate mode when the application buffer reaches a maximum capacity and the processor in the receiver enters an idle low power, low clock rate mode after the application buffer has reached the maximum capacity and the receiver protocol state machine has processed packets residing in the application buffer.

13. A receiver for managing energy usage of a processor in the receiver, comprising:

a protocol state machine to receive a packet from a transmitter over a data communication network and to process and verify the packet;

a processor coupled to the protocol state machine; and

an application buffer coupled to the protocol state machine to store the packet,

wherein the protocol state machine transmits and acknowledgment of receipt of the date packet to the transmitter, the protocol state machine manages a power level of the processor in the receiver based on a utilized capacity of the application buffer, the processor in the receiver switching to a high-power, high clock rate mode from a low power, low clock rate mode when the application buffer reaches a threshold.

14. The receiver of claim 13, wherein the application buffer and a timer cause periodic patterns in data packet receition, which are used to manage power and frequency of a processor in a transmitting device.

15. A receiver for managing energy usage of a processor, comprising:

a protocol state machine to receive a packet from a transmitter over a data communication network and to process and verify the packet;

a processor coupled to the receiver protocol state machine; and

an application buffer coupled to the protocol state machine to store the packet,

wherein the protocol state machine transmits an acknowledgment of receipt of the data packet to the transmitter and the protocol state machine manages a power level of the processor based on a utilized capacity of the application buffer and wherein the processor enters an idle low power, low clock rate mode after the application buffer has reached the maximum capacity and the receiver protocol state machine has processed packets residing in the application buffer.

16. A method of managing energy usage of a processor in a receiver, comprising:

receiving a data packet at a receiver protocol state machine, the data packet being transmitted from a transmitter protocol state machine over a data communication network;

depositing the data packet in an application buffer;

processing and verifying the data packet; and

transmitting an acknowledgment of receipt of the data packet to the transmitter protocol state machine, wherein the receiver protocol state machine manages the a power level of the processor in the receiver which is coupled to the receiver protocol state machine, based on a utilized capacity of the application buffer, the processor in the receiver switching to a high-power, high clock rate mode from a low power, low clock rate mode when the application buffer reaches a threshold.

17. The method of claim 16, wherein the application buffer and a timer cause periodic patterns in data packet reception, which are used to manage power and frequency of a processor in a transmitting device.

18. The method of claim 16, wherein the data communication network includes at least one of the Internet and an Intranet.

19. A method of managing energy usage of a processor in a receiver, comprising:

receiving a data packet at a receiver protocol state machine, the data packet being transmitted from a transmitter protocol state machine over a data communication network;

depositing the data packet in an application buffer;

processing and verifying the data packet; and

transmitting an acknowledgment of receipt of the data packet to the transmitter protocol state machine, wherein the receiver protocol state machine manages the a power level of the processor based on a utilized capacity of the application buffer, the processor enters a high power, high clock rate mode when the application buffer reaches a maximum capacity, and the processor enters an idle low power, low clock rate mode after the application buffer has reached the maximum capacity and the receiver protocol state machine has processed packets residing in the application buffer.

20. A method of managing energy usage of a processor in a transmitting device, comprising:

invoking a protocol state machine to send a packet across a data communication network to a receiver and waiting for an acknowledgment of receipt;

storing incoming packets that are to transmitted by the protocol state machine to the receiver in a buffer;

managing a power level of the processor in the transmitting device based on a utilized capacity of the buffer;

transmitting any of the packets in the buffer until the utilized capacity of the buffer reaches the threshold; and

switching the power level of the processor to a low power, low rate clock mode after the packets in the buffer have been transmitted.