Memory hub and access method having internal prefetch buffers
First Claim
1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the link interface, the memory device interface and the history logic unit, the memory sequencer being operable to transfer memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to generate and transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data from memory cells being accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface, the link interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer, the control unit further being responsive to the read memory request to transfer the read data from the prefetch buffer if the read data are stored in the prefetch buffer and to transfer the read data from the memory device interface if the read data are stored in the memory devices.
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Accused Products
Abstract
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.
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Citations
53 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the link interface, the memory device interface and the history logic unit, the memory sequencer being operable to transfer memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to generate and transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data from memory cells being accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface, the link interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer, the control unit further being responsive to the read memory request to transfer the read data from the prefetch buffer if the read data are stored in the prefetch buffer and to transfer the read data from the memory device interface if the read data are stored in the memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the memory device interface, the memory sequencer being operable to transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data from memory cells being accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory hub, comprising:
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a link interface receiving memory requests;
a memory device interface operable to output memory requests and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the link interface, the memory device interface and the history logic unit, the memory sequencer being operable to transfer memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to generate and transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data received responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface, the link interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer, the control unit further being responsive to the read memory request to transfer the read data from the prefetch buffer if the read data are stored in the prefetch buffer and to transfer the read data from the memory device interface if the read data are not stored in the prefetch buffer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A memory hub, comprising:
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a link interface receiving memory requests;
a memory device interface operable to output memory requests and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the memory device interface and the history logic unit, the memory sequencer being operable to transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer and to transfer the read data from the prefetch buffer responsive to determining that the read data are stored in the prefetch buffer. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A computer system, comprising:
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a central processing unit (“
CPU”
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a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising;
a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the link interface, the memory device interface and the history logic unit, the memory sequencer being operable to transfer memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to generate and transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data from memory cells being accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface, the link interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer, the control unit further being responsive to the read memory request to transfer the read data from the prefetch buffer if the read data are stored in the prefetch buffer and to transfer the read data from the memory device interface if the read data are stored in the memory devices. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A computer system, comprising:
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a central processing unit (“
CPU”
);
a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising;
a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a history logic unit coupled to the link interface to receive memory requests from the link interface, the history logic being operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests, the history logic unit generating prefetching suggestions indicative of the predicted addresses;
a memory sequencer coupled to the memory device interface and the history logic unit, the memory sequencer being operable to transfer prefetch requests to the memory device interface responsive to prefetching suggestions received from the history logic unit;
a prefetch buffer coupled to the memory device interface for receiving and storing read data from memory cells being accessed responsive to the prefetch requests; and
a data read control unit coupled to the memory device interface and the prefetch buffer, the data read control circuit being operable to determine from a read memory request received from the link interface if the read data are stored in the prefetch buffer and to transfer the read data from the prefetch buffer responsive to determining that the read data are stored in the prefetch buffer. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A method of reading data from a memory module, comprising:
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receiving memory requests for access to a memory device mounted on the memory module;
coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;
receiving read data responsive to the read memory requests;
predicting addresses that are likely to be accessed in the memory device based on the read memory requests, the address prediction being internal to the memory module;
generating prefetching suggestions indicative of the predicted addresses;
generating prefetch requests responsive to the prefetching suggestions;
coupling the prefetch requests to the memory device;
receiving prefetched read data responsive to the prefetch requests;
storing the prefetched read data in a prefetch buffer;
determining from a read memory request if the requested read data are stored in the prefetch buffer;
coupling the read data from the prefetch buffer if a determination has been made that the read data are stored in the prefetch buffer; and
coupling the read data from the memory device if a determination has not been made that the read data are stored in the prefetch buffer. - View Dependent Claims (41, 42, 43, 44, 45, 46)
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47. A method of reading data from a memory module, comprising:
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receiving memory requests for access to a memory device mounted on the memory module;
coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;
receiving read data responsive to the read memory requests;
predicting addresses that are likely to be accessed in the memory device based on the read memory requests, the address prediction being internal to the memory module;
generating prefetching suggestions indicative of the predicted addresses;
generating prefetch requests responsive to the prefetching suggestions;
coupling the prefetch requests to the memory device;
receiving prefetched read data responsive to the prefetch requests;
storing the prefetched read data in a prefetch buffer;
determining from a read memory request if the requested read data are stored in the prefetch buffer; and
coupling the read data from the prefetch buffer if a determination has been made that the read data are stored in the prefetch buffer. - View Dependent Claims (48, 49, 50, 51, 52, 53)
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Specification