Programmable processor and method for partitioned group shift

• US 7,260,708 B2
• Filed: 11/13/2003
• Issued: 08/21/2007
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/705,946
• Publication Number:
  US 20040103266A1
• Time in Patent Office: 1,377 Days
• Field of Search: 712/223, 712/22, 712/222
• US Class Current: 712/223
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.

Claims

1. A programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying both a shift amount and a register having a register width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width, the execution unit is operable to;

(i) shift a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and

(ii) provide the second plurality of data elements as a catenated result.

2. The processor of claim 1 wherein the catenated result is provided to a register.

3. The processor of claim 1 wherein the shift amount is contained in a register specified by the instruction.

4. The processor of claim 1 wherein the shift amount is contained in an immediate field of the instruction.

5. The processor of claim 1 wherein each data element in the first plurality of data elements has a sign bit in a most significant bit position and wherein the execution unit is further operable to fill a shift amount number of most significant bits in each of the second plurality of data elements with the sign bit from a respective data element in the first plurality of data elements.

6. The processor of claim 1 wherein the execution unit is further operable to fill a shift amount number of most significant bits in each of the second plurality of data elements with zeros.

7. The processor of claim 1 wherein the execution unit is further operable to fill a shift amount number of bits in each of the second plurality of data elements with a subfield from a respective location of the contents of an additional register.

8. The processor of claim 1 wherein the catenated result has a width of 128 bits.

9. The processor of claim 1 wherein the elemental width of each of the first plurality of data elements is 32 bits.

10. The processor of claim 1 wherein the elemental width of each of the first plurality of data elements is 16 bits.

11. The processor of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to the elemental width of each of the first plurality of data elements.

12. The processor of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to twice the elemental width of each of the first plurality of data elements.

13. The processor of claim 1 wherein an elemental width of each of the second plurality of data elements is equal to half the elemental width of each of the first plurality of data elements.

14. A method for shifting data in a programmable processor, the method comprising:

decoding a single instruction specifying both a shift amount and a register having a register width, the register containing a first plurality of data elements having an elemental width smaller than the register width, the number of data elements in the first plurality of data elements being inversely related to the elemental width, the shift amount configurable to an amount inclusively between zero and one less than the elemental width;

shifting a subfield of each of the first plurality of data elements by the shift amount to produce a second plurality of data elements; and

providing the second plurality of data elements as a catenated result.

15. The method of claim 14 wherein the catenated result is provided to a register.

16. The method of claim 14 wherein the shift amount is contained in a register specified by the instruction.

17. The method of claim 14 wherein the shift amount is contained in an immediate field of the instruction.

18. The method of claim 14 wherein each data element in the first plurality of data elements has a sign bit in a most significant bit position and wherein the method further comprises:

filling a shift amount number of most significant bits in each of the second plurality of data elements with the sign bit from a respective data element in the first plurality of data elements.

19. The method of claim 14 wherein the method further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with zeros.

20. The method of claim 14 wherein the method further comprises:

filling a shift amount number of bits in each of the second plurality of data elements with a subfield from a respective location of the contents of an additional register.

21. The method of claim 14 wherein the catenated result has a width of 128 bits.

22. The method of claim 14 wherein the elemental width of each of the first plurality of data elements is 32 bits.

23. The method of claim 14 wherein the elemental width of each of the first plurality of data elements is 16 bits.

24. The method of claim 14 wherein an elemental width of each of the second plurality of data elements is equal to the elemental width of each of the first plurality of data elements.

25. The method of claim 14 wherein an elemental width of each of the second plurality of data elements is equal to twice the elemental width of each of the first plurality of data elements.

26. A programmable processor comprising:

an instruction path;

a data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single group shift right instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register, the execution unit is operable to;

(i) for each of the plurality of data elements in the operand register, shift a subfield of the data element towards the least significant bit by the shift amount and fill a shift amount number of most significant bits with the sign bit of the respective data element to produce a second plurality of equal-sized data elements and (ii) provide the second plurality of data elements as a catenated result to the destination register.

27. The programmable processor set forth in claim 26 wherein the execution unit is operable to execute group shift right instructions on 16-bit, 32-bit and 64-bit signed integer data.

28. The programmable processor set forth in claim 27 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

29. The programmable processor set forth in claim 26 wherein the shift amount is contained in an immediate field of the instruction.

30. The programmable processor set forth in claim 26 wherein the shift amount is contained in a register specified by the instruction.

31. A programmable processor comprising:

an instruction path;

a data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single group shift right instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register, the execution unit is operable to;

(i) for each of the plurality of data elements in the operand register, shift a subfield of the data element towards the least significant bit by the shift amount and fill a shift amount number of most significant bits with zeros to produce a second plurality of equal-sized data elements and (ii) provide the second plurality of data elements as a catenated result to the destination register.

32. The programmable processor set forth in claim 31 wherein the execution unit is operable to execute group shift right instructions on 16-bit, 32-bit and 64-bit unsigned integer data.

33. The programmable processor set forth in claim 32 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

34. The programmable processor set forth in claim 31 wherein the shift amount is contained in an immediate field of the instruction.

35. The programmable processor set forth in claim 31 wherein the shift amount is contained in a register specified by the instruction.

36. A programmable processor comprising:

an instruction path;

a data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single group shift left instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register, the execution unit is operable to;

(i) for each of the plurality of data elements in the operand register, shift a subfield of the data element towards the most significant bit by the shift amount and fill a shift amount number of least significant bits with the sign bit of the respective data element to produce a second plurality of equal-sized data elements and (ii) provide the second plurality of data elements as a catenated result to the destination register.

37. The programmable processor set forth in claim 36 wherein the execution unit is operable to execute group shift left instructions on 16-bit, 32-bit and 64-bit signed integer data.

38. The programmable processor set forth in claim 37 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

39. The programmable processor set forth in claim 36 wherein the shift amount is contained in an immediate field of the instruction.

40. The programmable processor set forth in claim 36 wherein the shift amount is contained in a register specified by the instruction.

41. A method for shifting data in a programmable processor, the method comprising:

decoding a single group shift right instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register;

for each of the plurality of data elements in the operand register, shifting a subfield of the data element towards the least significant bit by the shift amount and fill a shift amount number of most significant bits with the sign bit of the respective data element to produce a second plurality of equal-sized data elements; and

providing the second plurality of data elements as a catenated result to the destination register.

42. The method set forth in claim 41 wherein the execution unit is operable to execute group shift right instructions on 16-bit, 32-bit and 64-bit signed integer data.

43. The method set forth in claim 42 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

44. The method set forth in claim 41 wherein the shift amount is contained in an immediate field of the instruction.

45. The method set forth in claim 41 wherein the shift amount is contained in a register specified by the instruction.

46. A method for shifting data in a programmable processor, the method comprising:

decoding a single group shift right instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register;

for each of the plurality of data elements in the operand register, shifting a subfield of the data element towards the least significant bit by the shift amount and fill a shift amount number of most significant bits with zeros to produce a second plurality of equal-sized data elements; and

providing the second plurality of data elements as a catenated result to the destination register.

47. The method set forth in claim 46 wherein the execution unit is operable to execute group shift right instructions on 16-bit, 32-bit and 64-bit unsigned integer data.

48. The method set forth in claim 47 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

49. The method set forth in claim 46 wherein the shift amount is contained in an immediate field of the instruction.

50. The method set forth in claim 46 wherein the shift amount is contained in a register specified by the instruction.

51. A method for shifting data in a programmable processor, the method comprising:

decoding a single group shift left instruction specifying a shift amount, an operand register containing a plurality of equal-sized data elements stored in partitioned fields of the operand register and a destination register;

for each of the plurality of data elements in the operand register, shifting a subfield of the data element towards the most significant bit by the shift amount and fill a shift amount number of least significant bits with the sign bit of the respective data element to produce a second plurality of equal-sized data elements; and

providing the second plurality of data elements as a catenated result to the destination register.

52. The method set forth in claim 51 wherein the execution unit is operable to execute group shift left instructions on 16-bit, 32-bit and 64-bit signed integer data.

53. The method set forth in claim 52 wherein the operand register is a 128-bit register and the destination register is a 128-bit register.

54. The method set forth in claim 51 wherein the shift amount is contained in an immediate field of the instruction.

55. The method set forth in claim 51 wherein the shift amount is contained in a register specified by the instruction.