Semiconductor device with speed binning test circuit and test method thereof

• US 7,260,754 B2
• Filed: 11/25/2003
• Issued: 08/21/2007
• Est. Priority Date: 01/07/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Hoi-Jin
• Primary Examiner(s): Lamarre; Guy
• Assistant Examiner(s): Trimmings; John P.
• Application Number:
  US10/720,123
• Publication Number:
  US 20040133830A1
• Time in Patent Office: 1,365 Days
• Field of Search: None
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.

Claims

1. A speed binning test circuit, comprising:

a plurality of circuit groups arranged along a boundary of a chip circuit, each circuit group including a different number of unit delay circuits with respect to each other;

a plurality of pads, each pad disposed between two adjacent circuit groups of the plurality of circuit groups, wherein each of the pads is connected to at least one output terminal of one of the two adjacent circuit groups and also connected to at least one input terminal of the other of the two adjacent circuit groups; and

wherein the circuit groups comprise combinational circuits.

2. The speed binning test circuit of claim 1, wherein the plurality of circuit groups include:

a first speed correlation circuit in which unit delay circuits of a first group are serially-connected to one another for delaying a received final delay signal and outputting a first delay signal;

a second speed correlation circuit in which unit delay circuits of a second group are serially-connected to one another for delaying the first delay signal and outputting a second delay signal;

a third speed correlation circuit in which unit delay circuits of a third group are serially-connected to one another for delaying the second delay signal and outputting a third delay signal; and

a fourth speed correlation circuit in which unit delay circuits of a fourth group are serially-connected to one another for delaying the third delay signal and outputting the final delay signal that is received by the first group of unit delay circuits.

3. The speed binning test circuit of claim 2, wherein the first through third delay signals, collectively, and the final delay signal have the same oscillation waveforms after a given time.

4. The speed binning test circuit of claim 3, wherein the given time represents a total signal delay time of a signal delayed through the first through fourth groups.

5. The speed binning test circuit of claim 1, wherein the ratio of numbers of unit delay circuits of the plurality of circuit groups are expressed by:

A;

B;

C;

D=a;

b;

c;

d,

wherein A denotes a number obtained by subtracting 1 from the numbers of unit delay circuits of a first group;

B denotes the number of Unit delay circuits of a second group;

C denotes the number of unit delay circuits of a third group;

D denotes a number of unit delay circuits of the fourth group, and

wherein a, b, c, and d represent different valued coefficients.

6. The speed binning test circuit of claim 5, wherein a, b, c, and d are different prime numbers.

7. The speed binning test circuit of claim 1, wherein the unit delay circuits are inverter circuits.

8. A semiconductor device, comprising:

a plurality of signal input/output pins;

a core circuit including logic that receives or outputs a signal via the plurality of signal input/output pins; and

a speed binning test circuit including;

a plurality of circuit groups, each circuit group including a different number of unit delay circuits with respect to each other arranged in a chain structure along the boundary of the core circuit,

a plurality of pads, each pad disposed between two adjacent circuit groups of the plurality of circuit groups, wherein each of the pads is connected to at least one output terminal of one of the two adjacent circuit groups and also connected to at least one input terminal of the other of the two adjacent circuit groups;

and

wherein the circuit groups comprise combinational circuits.

9. The semiconductor device of claim 8, wherein the speed binning test circuit comprises:

a first speed correlation circuit in which unit delay circuits of a first group are serially-connected to one another for delaying a received final delay signal and outputting a first delay signal;

a second speed correlation circuit in which unit delay circuits of a second group are serially-connected to one another for delaying the first delay signal and outputting a second delay signal;

a third speed correlation circuit in which unit delay circuits of a third group are serially-connected to one another for delaying the second delay signal and outputting a third delay signal; and

a fourth speed correlation circuit in which unit delay circuits of a fourth group are serially-connected to one another for delaying the third delay signal and outputting the final delay signal that is received by the first group of unit delay circuits.

10. The semiconductor device of claim 9, wherein the first through third delay signals, collectively, and the final delay signal have the same oscillation waveforms after a given time.

11. The semiconductor device of claim 10, wherein the given time represents a total signal delay time of a signal delayed through the first through fourth groups.

12. The semiconductor device of claim 8,

wherein the ratio of numbers of unit delay circuits of the plurality of circuit groups are expressed by:

A;

B;

C;

D=a;

b;

c;

d,

wherein A denotes a number obtained by subtracting 1 from the numbers of unit delay circuits of a first group;

B denotes the number of unit delay circuits of a second group;

C denotes the number of unit delay circuits of a third group;

D denotes a number of unit delay circuits of the fourth group, and

wherein a, b, c, and d represent different valued coefficients.

13. The semiconductor device of claim 12, wherein a, b, c, and d are different prime numbers.

14. The semiconductor device of claim 8, wherein the unit delay circuits are inverter circuits.

15. A speed binning test method, comprising:

delaying test signals through a plurality of successively connected circuit groups, each of the plurality of successively connected circuit groups including different number of unit delay circuits with respect to each other, that forms a chain structure on a chip,

monitoring on-chip-variations to determine total signal delay time through the chain structure at a plurality of pads, each pad disposed between two adjacent circuit groups of the plurality of circuit groups, wherein each of the pads is connected to at least one output terminal of one of the two adjacent circuit groups and also connected to at least one input terminal of the other of the two adjacent circuit groups; and

wherein the circuit groups comprise combinational circuits.

16. The method of claim 15, further comprising receiving the test signals from the circuit groups on the chip via a plurality of signal input/output pins.

17. The method of claim 15, wherein the delaying step further includes:

first delaying a received final delay signal and outputting a first delay signal in a first group of the plurality of successively connected circuit group;

second delaying the first delay signal and outputting a second delay signal in a second group of the plurality of successively connected circuit group;

third delaying the second delay signal and outputting a third delay signal in a third group of the plurality of successively connected circuit group; and

fourth delaying the third delay signal and outputting the final delay signal that is received by the first group in a fourth group of the plurality of successively connected circuit group.

18. The method of claim 17, wherein the monitoring step further includes monitoring on-chip variations by measuring oscillation waveforms.

19. The method of claim 18, wherein the first through third delay signals, collectively, and the final delay signal have the same oscillation waveforms after a given time.

20. The method of claim 19, wherein the given time represents a total signal delay time of a signal delayed through the first through fourth groups.

21. The method of claim 15,

wherein the ratio of numbers of unit delay circuits of the plurality of circuit groups are expressed by:

A;

B;

C;

D=a;

b;

c;

d,

wherein A denotes a number obtained by subtracting 1 from the numbers of unit delay circuits of a first group;

B denotes the number of unit delay circuits of a second group;

C denotes the number of unit delay circuits of a third group;

D denotes a number of unit delay circuits of the fourth group, and

wherein a, b, c, and d represent different valued coefficients.

22. The method of claim 21, wherein a, b, c, and d are different prime numbers.