Method and system for performing built-in self-test routines using an accumulator to store fault information
First Claim
1. A method for use with a memory array, said method comprising the steps of:
- (i) subjecting the memory array to a selectively variable stress condition;
(ii) testing the memory array to detect faulty memory locations therein;
(iii) generating fault information indicative of any faulty memory address locations detected by the testing operation;
(iv) cumulatively storing the fault information;
(v) defining a fault count based upon the cumulatively stored fault information;
(vi) comparing the fault count to a redundant memory count; and
(vii) iteratively repeating steps (i), (ii), (iii), (iv), (v) and (vi).
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Accused Products
Abstract
A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
62 Citations
22 Claims
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1. A method for use with a memory array, said method comprising the steps of:
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(i) subjecting the memory array to a selectively variable stress condition; (ii) testing the memory array to detect faulty memory locations therein; (iii) generating fault information indicative of any faulty memory address locations detected by the testing operation; (iv) cumulatively storing the fault information; (v) defining a fault count based upon the cumulatively stored fault information; (vi) comparing the fault count to a redundant memory count; and (vii) iteratively repeating steps (i), (ii), (iii), (iv), (v) and (vi). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for use with a memory array, said method comprising the steps of:
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(i) subjecting the memory array to a selectively variable stress condition; (ii) testing the memory array to detect faulty memory locations therein; (iii) generating fault information indicative of any faulty memory address locations detected by the testing operation; (iv) cumulatively storing the fault information; (v) identifying a quantity of faulty memory locations corresponding to the cumulatively stored fault information; and (vi) comparing the quantity of faulty memory locations to a quantity of redundant memory locations; and (vii) rejecting the memory array if the quantity of faulty memory locations exceeds the quantity of redundant memory locations, as indicated by the comparison operation; (viii) iteratively repeating steps (i), (ii), (iii), (iv), (v), (vi) and (vii). - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification