Power estimation employing cycle-accurate functional descriptions

• US 7,260,809 B2
• Filed: 03/31/2006
• Issued: 08/21/2007
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Laboratories America Inc (NEC Corporation)
• Inventors: Zhong, Lin, Ravi, Srivaths, Raghunathan, Anand, Jha, Niraj K.
• Primary Examiner(s): Whitmore; Stacy A
• Application Number:
  US11/278,182
• Publication Number:
  US 20070022395A1
• Time in Patent Office: 508 Days
• Field of Search: 716 4- 5, 716/18
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.

Claims

1. A method of estimating the power of a circuit, said method comprising the steps of:

generating a Register-Transfer-Level aware, Cycle-Accurate Functional Description (RTL-CAFD) of the circuit, wherein said CAFD does not include an explicit manifestation of the circuit structure;

simulating the generated RTL-CAFD in conjunction with a power model library of various RTL components; and

producing a power estimate from the simulation.

2. The method of claim 1, wherein said generating step further comprises the steps of:

producing a CAFD description of the circuit; and

synthesizing the CAFD into an RTL-CAFD.

3. The method of claim 2 wherein said synthesizing step further comprises the steps of:

assigning functional elements to RTL components in the CAFD description.

4. The method of claim 3 wherein said CAFDs are state-based CAFDs.

5. The method of claim 4 wherein each of said functional elements belongs to a unique state.

6. The method of claim 1 wherein each CAFD describes the behavior of the circuit for each cycle of its operation.

7. The method of claim 1 wherein the CAFD includes one or more virtual components.

8. The method of claim 7 wherein said virtual components include component I/O values in current and previous cycles.

9. A method of producing power estimates of a circuit, said method comprising the steps of:

generating a Cycle-Accurate Functional Description (CAFD) of the circuit which does not contain an explicit manifestation of the circuit structure;

simulating the generated CAFD; and

producing a power estimate from the simulation.

10. The method of claim 9, further comprising the steps of:

preprocessing the CAFD description of the circuit so that each functional element is given a unique identifier.

11. The method of claim 10, further comprising the steps of:

synthesizing an RTL description of the circuit from the CAFD description.

12. The method of claim 11 further comprising the steps of:

extracting RTL information from the CAFD description wherein said extraction includes the correlation of RTL components to CAFD functional elements.

13. The method of claim 12 further comprising the steps of:

generating a mapping table to map the functional element into RTL components.

14. The method of claim 13 further comprising the steps of:

generating a select signal table for specifying which data inputs are selected in each control state.

15. The method of claim 14 further comprising the steps of:

instantiating a virtual component for each functionally-explicit RTL component and each multiplexer to keep a record of previous and current input vectors.

16. The method of claim 15 further comprising the steps of:

determining idle-cycle inputs to a component.

17. The method of claim 9 further comprising the steps of:

determining a set of important cycles for which to determine the power estimate.