Active pixel sensor cell with integrating varactor and method for using such cell

• US 7,262,401 B2
• Filed: 08/01/2006
• Issued: 08/28/2007
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Eastman Kodak Company
• Inventors: Mirgorodski, Yuri, Hopper, Peter J., Lindorfer, Philipp, Poulter, Mark W.
• Primary Examiner(s): Epps; Georgia
• Assistant Examiner(s): Wyatt; Kevin
• Application Number:
  US11/496,951
• Publication Number:
  US 20060266925A1
• Time in Patent Office: 392 Days
• Field of Search: 250/208.1
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

Claims

1. An image sensor including an array of active pixel sensor cells, wherein each of the cells includes:

at least one photodiode configured to be exposed to photons during an exposure interval including at least two subexposure intervals;

reset circuitry coupled to the photodiode; and

an integrating varactor, coupled between the photodiode and a storage node, and configured so that an exposure charge accumulates at the storage node during the exposure interval;

wherein, in each of the cells, the reset circuitry is configured to reset the photodiode during each of a sequence of reset intervals, each of the reset intervals precedes a different one of the subexposure intervals, and the photodiode is configured so that a subexposure charge accumulates at the first node during each of the subexposure intervals,

wherein the reset intervals are sufficiently short relative to the subexposure intervals and the varactor capacitance is sufficiently large relative to the first capacitance that the exposure charge at the end of a final one of the subexposure intervals is indicative of the sum of the subexposure charges accumulated at the first node during all the subexposure intervals.

2. The sensor of claim 1, wherein the cells are arranged in rows and columns of cells, said sensor also including:

a set of column lines, wherein each of the columns of cells is coupled to a different one of the column lines, and the cells of each of the rows are coupled to different ones of the column lines; and

readout circuitry, wherein the column lines are coupled to the readout circuitry, and the readout circuitry is configured to read out all the cells of the array after an exposure interval.

3. The sensor of claim 1, wherein, in each of the cells, the photodiode has a first node, the varactor is coupled between the first node and the storage node, the cell has a first capacitance at the first node, the varactor provides a varactor capacitance at the storage node, and the varactor capacitance is much greater than the first capacitance.

4. The sensor of claim 1, wherein, in each of the cells, the photodiode has a first node, the reset circuitry is an MOS transistor having a channel terminal coupled to the first node, and the varactor is coupled between the first node and the storage node.

5. The sensor of claim 4, wherein, in each of the cells, the first node is a non-grounded terminal of the photodiode.

6. The sensor of claim 1, wherein each of the cells also includes:

output circuitry, coupled to the storage node and an output node, and configured to assert at the output node an output signal indicative of the storage node'"'"'s potential.

7. The sensor of claim 6, wherein, in each of the cells, the output circuitry includes an MOS transistor having a gate coupled to the storage node.

8. The sensor of claim 1, wherein each of the cells also includes:

output circuitry, coupled to the storage node and an output node, and configured to assert at the output node an output signal indicative of the charge on the storage node.

9. The sensor of claim 1, wherein, in each of the cells, the varactor is a field effect, gated junction device.

10. The sensor of claim 9, wherein, in each of the cells, the photodiode has a first node, the reset circuitry is a transistor having a channel terminal coupled to the first node, and the varactor is an MOS transistor whose channel is coupled between the first node and the storage node.

11. The sensor of claim 9, wherein, in each of the cells, the varactor is biased during operation such that one of a source region and a drain region of the varactor provides the varactor capacitance at the storage node.

12. The sensor of claim 11, wherein, in each of the cells, the varactor is an NMOS transistor that is biased during operation such that a drain region of said varactor provides the varactor capacitance at the storage node.