Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon

• US 7,262,513 B2
• Filed: 06/30/2005
• Issued: 08/28/2007
• Est. Priority Date: 06/18/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Mathew, Ranjan J.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US11/172,717
• Publication Number:
  US 20050258549A1
• Time in Patent Office: 789 Days
• Field of Search: 257/786, 257/779
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45164 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48847 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/2075 : larger or equal to 1 micron less than 10 microns
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns

Abstract

A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.

Claims

1. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having

an electrical connection to the circuitry through an aperture in the insulating layer and

a peripheral bonding zone region extending over the insulating layer; and

an excluded zone.

9. The apparatus of claim 1, wherein the circuitry includes at least a portion of a processor, the apparatus further comprising:

a memory operatively coupled to the processor;

an input/output system, including a display unit, operatively coupled to the processor; and

a power supply operatively coupled to the processor.

10. The apparatus of claim 1, wherein the circuitry includes at least a portion of a telecommunications circuit, the apparatus further comprising:

an antenna operatively coupled to the telecommunications circuit;

an input/output system, including a display unit, operatively coupled to the telecommunications circuit; and

a power supply operatively coupled to the telecommunications circuit.

2. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the insulating layer is compliant.

3. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the plurality of pads is both suitable for solder-ball connections and suitable for wirebond connections.

4. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the aperture is centered on the first pad.

5. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the aperture is offset to an edge of the first pad.

6. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the bonding zone for wirebonding is exclusively over the insulating layer outside of the aperture.

7. The apparatus of claim 6, wherein the first pad is circular in shape.

8. The apparatus of claim 6, wherein the first pad is rectangular in shape.

11. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads having an electrical connection to the circuitry through a plurality of apertures in the insulating layer, the plurality of electrical connection pads including a peripheral bonding zone region extending over the insulating layer and an excluded bonding zone region.

13. The apparatus of claim 11, wherein the plurality of pads are cylindrical in shape.

14. The apparatus of claim 11, wherein the plurality of pads are include a rectangular wirebond surface.

15. The apparatus of claim 11, wherein at least one of the plurality of pads includes a top surface further comprising:

a wirebond target zone; and

a wirebond excluded zone.

12. An apparatus comprising:

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face;

a plurality of electrical connection pads having an electrical connection to the circuitry through a plurality of apertures in the insulating layer, the plurality of electrical connection pads including a peripheral bonding zone region extending over the insulating layer; and

a component with wire leads bonded to the plurality of electrical connection pads.

16. The apparatus of claim 12, further comprising a component having solderballs attached to the substrate.

17. The apparatus of claim 12, further comprising:

a first component;

and a second component, wherein the first component and the second component are stacked and attached to the substrate.

18. A system comprising:

an apparatus further comprising;

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer and an excluded bonding zone region; and

a display, the apparatus communicatively coupled to the display for sending inputs and receiving outputs from the display.

19. A system comprising:

an apparatus further comprising;

an electronics chip having a substrate with a first face having circuitry thereon;

an electrically insulating layer deposited on at least a portion of the first face; and

a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer and, wherein the circuitry includes at least a portion of a processor.