Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
First Claim
1. An apparatus comprising:
- an electronics chip having a substrate with a first face having circuitry thereon;
an electrically insulating layer deposited on at least a portion of the first face; and
a plurality of electrical connection pads including a first pad, the first pad havingan electrical connection to the circuitry through an aperture in the insulating layer anda peripheral bonding zone region extending over the insulating layer; and
an excluded zone.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.
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Citations
19 Claims
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1. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer; and
an excluded zone. - View Dependent Claims (9, 10)
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2. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the insulating layer is compliant.
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3. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the plurality of pads is both suitable for solder-ball connections and suitable for wirebond connections.
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4. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the aperture is centered on the first pad.
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5. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the aperture is offset to an edge of the first pad.
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6. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer, wherein the bonding zone for wirebonding is exclusively over the insulating layer outside of the aperture. - View Dependent Claims (7, 8)
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11. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads having an electrical connection to the circuitry through a plurality of apertures in the insulating layer, the plurality of electrical connection pads including a peripheral bonding zone region extending over the insulating layer and an excluded bonding zone region. - View Dependent Claims (13, 14, 15)
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12. An apparatus comprising:
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an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; a plurality of electrical connection pads having an electrical connection to the circuitry through a plurality of apertures in the insulating layer, the plurality of electrical connection pads including a peripheral bonding zone region extending over the insulating layer; and a component with wire leads bonded to the plurality of electrical connection pads. - View Dependent Claims (16, 17)
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18. A system comprising:
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an apparatus further comprising; an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer and an excluded bonding zone region; and a display, the apparatus communicatively coupled to the display for sending inputs and receiving outputs from the display.
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19. A system comprising:
an apparatus further comprising; an electronics chip having a substrate with a first face having circuitry thereon; an electrically insulating layer deposited on at least a portion of the first face; and a plurality of electrical connection pads including a first pad, the first pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer and, wherein the circuitry includes at least a portion of a processor.
Specification