Resource matrix, system, and method for operating same

• US 7,262,620 B2
• Filed: 10/31/2005
• Issued: 08/28/2007
• Est. Priority Date: 10/31/2005
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: de la Puente, Edmundo, Hart, Alan D.
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): Chan; Emily Y
• Application Number:
  US11/264,577
• Publication Number:
  US 20070096757A1
• Time in Patent Office: 666 Days
• Field of Search: 324/761, 324/763
• US Class Current: 324/756.04
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

In one embodiment, a resource matrix is provided with a first set of pins, a second set of pins, and at least one programmable switching circuit. The first set of pins electrically couples the resource matrix with a tester resource. The second set of pins electrically couples the resource matrix with a plurality of test areas. The at least one programmable switching circuit selectively couples each one of the first set of pins to different ones of the second set of pins. In one embodiment, the at least one programmable switching circuit includes a set of multiplexers. In another embodiment, the at least one programmable switching circuit includes a set of LIMMS. In another embodiment, a system is disclosed for testing a plurality of test areas with a tester resource and a resource matrix. Methods for routing signals between a tester resource and plurality of test areas are also disclosed.

Claims

1. A resource matrix, comprising:

a first set of pins for electrically coupling the resource matrix with a tester resource;

a second set of pins for electrically coupling the resource matrix with a plurality of test areas; and

at least one programmable switching circuit to electrically couple each one of the first set of pins to different ones of the second set of pins, a set of LIMMS in the at least one programmable switching circuit, and the LIMMS having a connection to one of the first set of pins and a set of multiple connections to the second set of pins, wherein the LIMMS couples the one of the first set of pins to selected ones of the second set of pins.

2. The resource matrix of claim 1, wherein the at least one programmable switching circuit has one set of LIMMS for each one of the first set of pins coupling the resource matrix to the tester resource.

3. The resource matrix of claim 1, further comprising a control system operably associated with each one of the set of LIMMS, wherein the control system controls operation of each one of the set of LIMMS.

4. The resource matrix of claim 1, wherein the plurality of test areas comprise a multi-chip package, wherein the plurality of test areas are disposed on a plurality of individual chips of the multi-chip package, and wherein the at least one programmable switching circuit selectively couples each one of the second set of pins to different individual chips of the multi-chip package.

5. The resource matrix of claim 1, wherein the plurality of test areas comprise a plurality of multi-chip packages, wherein the plurality of test areas are disposed on a plurality of individual chips of the plurality of multi-chip packages, and wherein the at least one programmable switching circuit selectively couples each one of the second set of pins to one of the plurality of individual chips of the plurality of multi-chip packages.

6. The resource matrix of claim 1, wherein at least two LIMMS of the set of LIMMS are stacked so as to provide a substantially direct route between the tester resource and the plurality of test areas.

7. The resource matrix of claim 1, wherein the set of LIMMS provide a high speed, high fidelity connection for bandwidths of up to 20 Ghz between the tester resource and the plurality of test areas.

8. A system, comprising:

a tester resource for testing a plurality of test areas having an exposed set of pins for coupling the tester resource to a resource matrix; and

the resource matrix, comprising;

a first set of pins for electrically coupling the resource matrix with the tester resource via the exposed set of pins;

a second set of pins for electrically coupling the resource matrix with the plurality of test areas; and

at least one programmable switching circuit to electrically couple each one of the first set of pins to different ones of the second set of pins, a set of LIMMS in the at least one programmable switching circuit, and the LIMMS having a connection to one of the first set of pins and a set of multiple connections to the second set of pins, wherein the LIMMS couples the one of the first set of pins to selected ones of the second set of pins.

9. The system of claim 8, further comprising a control system operably associated with the resource matrix for controlling operation of the at least one programmable switching circuit.

10. The system of claim 8, wherein the at least one programmable switching circuit has one set of LIMMS for each one of the first set of pins coupling the resource matrix to the tester resource.

11. The system of claim 8, wherein the plurality of test areas comprise a multi-chip package, wherein the plurality of test areas are disposed on a plurality of individual chips of the multi-chip package, and wherein the at least one programmable switching circuit selectively couples each one of the second set of pins to different individual chips of the multi-chip package.

12. The system of claim 8, wherein the plurality of test areas comprise a plurality of multi-chip packages, wherein the plurality of test areas are disposed on a plurality of individual chips of the plurality of multi-chip packages, and wherein the at least one programmable switching circuit selectively couples each one of the second set of pins to one of the plurality of individual chips of the plurality of multi-chip packages.

13. The system of claim 8, wherein at least two LIMMS of the set of LIMMS are stacked so as to provide a substantially direct route between the tester resource and the plurality of test areas.

14. The system of claim 8, wherein the set of LIMMS provide a high speed, high fidelity connection for bandwidths of up to 20 Ghz between the tester resource and the plurality of test areas.

15. A method, comprising:

electrically coupling a resource matrix with a tester resource via a first set of pins;

electrically coupling the resource matrix with a plurality of test areas via a second set of pins; and

routing signals between the tester resource and the plurality of test areas via at least one programmable switching circuit of the resource matrix, wherein the at least one programmable switching circuit selectively couples each one of the first set of pins to different ones of the second set of pins, wherein a set of LIMMS is provided in the at least one programmable switching circuit, and the LIMMS has a connection to one of the first set of pins and a set of multiple connections to the second set of pins, and wherein the set of LIMMS couples the one of the first set of pins to selected ones of the second set of pins.

16. The method of claim 15, further comprising activating a control system before routing signals between the tester resource and the plurality of test areas to control selectively coupling each one of the first set of pins to different ones of the second set of pins.

17. The method of claim 15, wherein the routing signals between the tester resource and the plurality of test areas via at least one programmable switching circuit of the resource matrix includes at least two LIMMS of the set of LIMMS stacked so as to provide a substantially direct route between the tester resource and the plurality of test areas.

18. The method of claim 15, wherein the routing signals between the tester resource and the plurality of test areas via at least one programmable switching circuit of the resource matrix includes the set of LIMMS with a high speed, high fidelity connection for bandwidths of up to 20 Ghz between the tester resource and the plurality of test areas.