Wafer-level package for integrated circuits

• US 7,262,622 B2
• Filed: 03/24/2005
• Issued: 08/28/2007
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Memsic Semiconductor (Wuxi) Co., Ltd. (MZ Investment Holdings Ltd.)
• Original Assignee: Memsic Incorporated (MZ Investment Holdings Ltd.)
• Inventors: Zhao, Yang
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US11/088,633
• Publication Number:
  US 20060216856A1
• Time in Patent Office: 887 Days
• Field of Search: None
• US Class Current: 438/110
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1627 stacked type assemblies, e.g. stacked multi-cavities

Abstract

A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

Claims

1. A method of wafer-level packaging an integrated circuit (IC) die, comprising:

providing an IC wafer comprising a plurality of die and at least one electrical contact point associated with each die;

providing a first semiconductor cap wafer;

forming electrically conductive paths through the first semiconductor cap wafer at positions corresponding to respective ones of the electrical contact points on the IC wafer, such that each electrically conductive path extends from a first side of the first semiconductor cap wafer to a second side of the first semiconductor cap wafer and is insulated from at least a portion of the first semiconductor cap wafer; and

before cutting the die from the IC wafer, attaching the first semiconductor cap wafer to the IC wafer, such that the ends of the conductive paths on the first side of the first semiconductor cap wafer are electrically connected to the respective electrical contact points on the IC wafer.

2. The method of claim 1, wherein forming each electrically conductive path comprises:

drilling a hole through the first semiconductor cap wafer;

forming an insulating layer on the inside wall of the drilled hole, thereby defining an insulated passage through the first semiconductor cap wafer; and

filling the insulated passage with an electrically conductive material.

3. The method of claim 2, wherein forming the insulating layer on the inside wall of the drilled hole comprises thermally growing the insulating layer.

4. The method of claim 2, wherein forming the insulating layer on the inside wall of the drilled hole comprises thermally growing a layer of SiO2 or SIN.

5. The method of claim 2, wherein forming the insulating layer on the inside wall of the drilled hole comprises vapor depositing the insulating layer.

6. The method of claim 2, wherein filling each insulated passage comprises:

pressing a mixture of powdered metal alloy paste containing an organic solvent into the insulated passage; and

subsequently burning away the organic solvent and leaving a hardened metal alloy.

7. The method of claim 2, wherein filling each insulated passage comprises filling the insulated passage with metal.

8. The method of claim 2, wherein filling each insulated passage comprises electroplating the insulated passage with metal.

9. The method of claim 2, wherein filling each insulated passage comprises filling the insulated passage with solder.

10. The method of claim 2, wherein filling each insulated passage comprises filling the insulated passage with AuSn.

11. The method of claim 2, wherein forming each insulated electrically conductive path further comprises:

forming an insulating layer on at least a portion of the second side of the first semiconductor cap wafer adjacent the drilled hole; and

forming an electrically conductive package contact pad on at least a portion of the insulating layer and in contact with one end of the electrically conductive material in the insulated passage.

12. The method of claim 2, wherein drilling the hole through the first semiconductor cap wafer comprises etching the hole.

13. The method of claim 2, wherein drilling the hole through the first semiconductor cap wafer comprises laser drilling the hole.

14. The method of claim 1, wherein providing the first semiconductor cap wafer comprises forming a spacer on the first side of the first semiconductor cap wafer.

15. The method of claim 1, wherein providing the IC wafer comprises forming a spacer on the IC wafer.

16. The method of claim 1, wherein providing the first semiconductor cap wafer comprises forming at least one cavity in the first side of the first semiconductor cap wafer.

17. The method of claim 1, wherein attaching the first semiconductor cap wafer to the IC wafer comprises sealing each of at least some of the die against infiltration through a gap between the IC wafer and the first semiconductor cap wafer.

18. The method of claim 17, wherein sealing the die comprises forming a glass frit on the cap wafer or on the IC wafer.

19. The method of claim 17, wherein sealing the die comprises forming a metal seal on the cap wafer or on the IC wafer.

20. The method of claim 1, further comprising thinning the first semiconductor cap wafer.

21. The method of claim 20, wherein thinning the first semiconductor cap water comprises lapping the first semiconductor cap wafer.

22. The method of claim 1, further comprising thinning the IC wafer.

23. The method of claim 22, wherein thinning the IC wafer comprises lapping the IC wafer.

24. The method of claim 1, further comprising dividing the first semiconductor cap wafer into a plurality of IC caps by cutting the first semiconductor cap wafer between pairs of the plurality of die.

25. The method of claim 24, further comprising singulating at least some of the die by cutting the die from the IC wafer.

26. The method of claim 1, wherein providing the IC wafer comprises providing an IC wafer fabricated of a material other than silicon.

27. The method of claim 1, wherein providing the IC wafer comprises providing an IC wafer fabricated of GaAs.

28. The method of claim 1, wherein providing the first semiconductor cap wafer comprises providing a cap wafer fabricated of Si.

29. The method of claim 1, wherein providing the first semiconductor cap wafer comprises providing a cap wafer fabricated of GaAs.

30. The method of claim 1, wherein providing the first semiconductor cap wafer comprises providing a cap wafer fabricated of GaN.

31. The method of claim 1, further comprising:

providing a second semiconductor cap wafer;

forming electrically conductive paths through the second semiconductor cap wafer at positions corresponding to respective ones of the electrically conductive paths through the first silicon wafer, such that each electrically conductive path through the second silicon wafer extends from a first side of the second semiconductor cap wafer to a second side of the second semiconductor cap wafer and is insulated from at least a portion of the second semiconductor cap wafer; and

before cutting the die from the IC wafer, attaching the second semiconductor cap wafer to the first semiconductor cap wafer, such that the ends of the conductive paths on the first side of the second semiconductor cap wafer are electrically connected to the respective electrically conductive paths through the first semiconductor cap wafer.

32. The method of claim 31, wherein forming each electrically conductive path comprises:

drilling a hole through the respective semiconductor cap wafer;

forming an insulating layer on the inside wall of the drilled hole, thereby defining an insulated passage through the respective semiconductor cap wafer; and

filling the insulated passage with an electrically conductive material.

33. The method of claim 32, wherein forming each insulated electrically conductive path on the second semiconductor cap wafer further comprises:

forming an insulating layer on at least a portion of the second side of the second semiconductor cap wafer adjacent the drilled hole; and

forming an electrically conductive package contact pad on at least a portion of the insulating layer and in contact with one end of the electrically conductive material in the insulated passage.