AC sensing for a resistive memory

• US 7,263,017 B2
• Filed: 07/07/2006
• Issued: 08/28/2007
• Est. Priority Date: 10/09/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Voshell, Thomas W.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/481,957
• Publication Number:
  US 20060250872A1
• Time in Patent Office: 417 Days
• Field of Search: 365/207, 365/148, 365/189.07
• US Class Current: 365/207
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding to the logic sate of the memory cell.

Claims

1. An apparatus for sensing a logic state of a memory cell, comprising:

a control circuit providing a control signal to said memory cell, said control signal controlling when said memory cell is sensed;

a switching circuit that receives a cellplate count signal and a bit count signal provided by said control circuit, said switching circuit further receiving a cellplate line signal and a bit line signal from said memory cell, said switching circuit producing a first output signal and a second output signal; and

a comparison circuit receiving said first and second output signals and outputting a signal corresponding to the logic state of said memory cell.

2. The apparatus according to claim 1, wherein said control circuit comprises:

a cellplate counter that produces said cellplate count signal;

a digit counter that produces said bit count signal; and

an exclusive-or (XOR) gate that produces said control signal.

3. The apparatus according to claim 2, wherein said control circuit comprises:

a first inverter for receiving said celiplate count and producing an inverted celiplate count signal and applying said inverted cellplate count signal to said switching circuit; and

a second inverter for receiving said bit count signal and producing an inverted bit count signal and applying said inverted bit count signal to said switching circuit.

4. The apparatus according to claim 3, wherein said comparison circuit further comprises:

a third inverter for receiving said inverted cellplate count signal and producing an inverted signal;

a first multiplexer for receiving said inverted signal, said inverted cellplate count signal, said first output signal, and said second output signal, said first multiplexer producing a third output signal;

a second multiplexer for receiving said inverted signal, said inverted cellplate count signal, said first output signal, and said second output signal, said second multiplexer producing a fourth output signal; and

a switched capacitor sensing amplifier for selecting one of said first output signal and said second output signal, said selected one of said first output signal and said second output signal corresponding to said logic state of said memory cell.

5. The apparatus according to claim 1, wherein said comparison circuit comprises a switched capacitor sensing amplifier for selecting one of said first output signal and said second output signal, said selected one of said first output signal and said second output signal corresponding to the logic state of said memory cell.

6. The apparatus according to claim 1, wherein said switching circuit comprises:

a first inverter for receiving said cellplate count and producing an inverted celiplate count signal and applying said inverted celiplate count signal to said switching circuit;

a second inverter for receiving said bit count signal and producing an inverted bit count signal and applying said inverted bit count signal to said switching circuit;

a third inverter for receiving said inverted celiplate count signal and producing an inverted signal;

a first multiplexer for receiving said inverted signal, said inverted cellplate count signal, said first output signal, and said second output signal, said first multiplexer producing a third output signal; and

a second multiplexer for receiving said inverted signal, said inverted cellplate count signal, said first output signal, and said second output signal, said second multiplexer producing a fourth output signal.

7. A memory device comprising:

an array of memory cells;

a cellplate line common across said array of memory cells; and

an apparatus for sensing a logic state of one of said memory cells, said apparatus conlprising;

first and second sensing lines between which are connected to a memory element having at least two resistive memory states,

switching circuitry that provides sensing current through the memory element, and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

8. A processing system, comprising:

a processor; and

a memory device coupled to said processor via a bus, said memory device comprising;

an array of memory cells,

a cellplate line common across said array of memory cells, and

an apparatus for sensing a logic state of one of said memory cells, said apparatus comprising;

first and second sensing lines between which are connected a memory element having at least two resistive memory states;

switching circuitry that provides sensing current through the memory element; and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

9. An integrated circuit comprising:

a memory device, said memory device comprising;

an array of memory cells,

a cellplate line common across said array of memory cells, and

an apparatus for sensing a logic state of one of said memory cells, said apparatus comprising;

first and second sensing lines between which are connected a memory element having at least two resistive memory states;

switching circuitry that provides sensing current through the memory element; and

output circuitry that receives said sensing current and, in response, provides an output signal indicating a resistance state of said memory element.

10. A processing system, comprising:

a processor; and

a memory device coupled to said processor via a bus, said memory device comprising;

an array of memory cells,

a cellplate line common across said array of memory cells, and

a control circuit providing a control signal, said control signal controlling when said memory cell is sensed;

a switching circuit that receives a celiplate count signal and a bit count signal provided by said control circuit, said switching circuit further receiving a ceilpiate line signal and a bit line signal from said memory cell, said switching circuit producing a first output signal and a second output signal; and

a comparison circuit receiving said first and second output signals and outputting a signal corresponding to the logic state of said memory cell.