Architecture of an integrated circuit for streaming media over wireless networks

• US 7,263,080 B1
• Filed: 04/15/2006
• Issued: 08/28/2007
• Est. Priority Date: 04/15/2006
• Status: Active Grant

• Current Assignee: Huwomobility, Inc.
• Original Assignee: RDW Incorporated
• Inventors: Chang, Chung-Hsing, Hsiung, Ted, Zhu, Robin Yubin
• Primary Examiner(s): Milord; Marceau
• Application Number:
  US11/279,881
• Time in Patent Office: 500 Days
• Field of Search: 370/348, 370/337, 370/328, 370/474, 375/354, 375/360, 711/104
• US Class Current: 370/328
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 27/2628 Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators H04L27/2634 takes precedence
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals

Abstract

An integrated circuit for streaming media over wireless networks is disclosed. The integrated circuit includes a media module that is designed to process media data. When non-media data is in, switching means is provided to avoid the non-media data being processed in the media module. One of important features in the integrated circuit is the underlying designs that are capable of facilitating wireless communication in different wireless networks. In one embodiment, a baseband processor is provided to facilitate wireless communications in more than one standard. The baseband processor is uniquely designed to facilitate wireless communications in a Wi-Fi network as well as a WiMAX network. As a result, same chips may be used to stream media data across different wireless networks.

Claims

1. An integrated circuit comprising:

a baseband processor capable of facilitating wireless communication via a RF interface in more than one wireless standards, wherein the baseband processor includes a plurality of functional blocks to process signals that are received or to be transmitted; and

a mode controller configured to control at least one of the functional blocks so the baseband processor performs to facilitate wireless communications in more than one wireless communication standards;

a media module designed for processing media data that is coupled to or from the baseband processor; and

switching means for avoiding non-media data being processed in the media module.

2. The integrated circuit as recited in claim 1, wherein the media module includes a codec that converts digitized video and audio signals to video and audio data according to a video standard.

3. The integrated circuit as recited in claim 2, wherein the video and audio data is processed in an application specific QoS control processing unit before being processed in the baseband processor.

4. The integrated circuit as recited in claim 1, wherein the media module includes a codec that converts video and audio data from the baseband processor to digitized video and audio signals according to a video standard.

5. The integrated circuit as recited in claim 4, wherein the video and audio data is processed in an application specific QoS control processing unit before being processed in the codec.

6. The integrated circuit as recited in claim 1, wherein the mode controller is configured to provide a first mode and a second mode, the integrated circuit supports Wi-Fi communication when the mode controller commands the first mode, the integrated circuit supports WiMAX communication when the mode controller commands the second mode.

7. The integrated circuit as recited in claim 6, wherein the functional blocks includes a RS codec that is deactivated when the mode controller commands the first mode.

8. The integrated circuit as recited in claim 7, wherein the RS codec is coupled between a scrambler and a convolution encoder, but signals are coupled between the scrambler and the convolution encoder.

9. The integrated circuit as recited in claim 8, wherein a multiplexer is provided to ensure that signals are received from the scrambler.

10. The integrated circuit as recited in claim 6, wherein the functional blocks includes a RS codec that is activated when the mode controller commands the second mode.

11. The integrated circuit as recited in claim 10, wherein the RS codec is coupled between a scrambler and a convolution encoder, and signals are coupled from the RS codec to the convolution encoder.

12. The integrated circuit as recited in claim 11, wherein a multiplexer is provided to ensure that signals are received from the RS codec.

13. The integrated circuit as recited in claim 6, wherein the functional blocks include

at least a FIFO buffer;

a first circuit, coupled to the FIFO buffer, performing either scramblering or unscramblering;

a second circuit performing either convolution encoding or Viterbi decoding;

a RS codec coupled between the first circuit and the second circuit;

a third circuit performing either interleaving or de-interleaving;

a forth circuit performing either modulating or demodulating, wherein the third circuit couples the second circuit to the forth circuit;

an FFT engine coupled to the firth circuit; and

a filter to ensure outgoing signals compliant with a communication standard, and filter out unwanted signals from incoming signals.

14. The integrated circuit as recited in claim 13 further including an AGC control circuit to control an RF interface to ensure that integrated circuit operates in a link-based mode or a packet-based mode.

15. The integrated circuit as recited in claim 13, wherein the mode controller is configured to provide a first mode and a second mode, the integrated circuit supports Wi-Fi communication when the mode controller commands the first mode, the integrated circuit supports WiMAX communication when the mode controller commands the second mode.

16. The integrated circuit as recited in claim 15, wherein the RS codec is activated or deactivated in response to the mode controller.

17. The integrated circuit as recited in claim 16, wherein a multiplexer is used to select signals to facilitate the Wi-Fi communication or the WiMAX communication.

18. The integrated circuit as recited in claim 15, wherein the mode controller is provided to control an operation mode of the integrated circuit, the mode controller receives a set of parameters from a memory in responding to a setting by a user to determine which mode the integrated circuit shall be operating.

19. The integrated circuit as recited in claim 15, wherein the mode controller is provided to control an operation mode of the integrated circuit, the mode controller is configured to determine automatically which mode the integrated circuit shall be operating in responding to what type of signals is being received.