Inquiring apparatus and method thereof

• US 7,263,564 B2
• Filed: 06/21/2004
• Issued: 08/28/2007
• Est. Priority Date: 09/03/2003
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Wang, Jar-Haur, Chen, Yung-Huei
• Primary Examiner(s): Sparks; Donald
• Assistant Examiner(s): PATEL, NIKETA I
• Application Number:
  US10/873,011
• Publication Number:
  US 20050060593A1
• Time in Patent Office: 1,163 Days
• Field of Search: 710/18, 710/19, 713/322, 713/323
• US Class Current: 710/19
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices

Abstract

An inquiring apparatus and method thereof is provided for assisting the CPU to inquire the state of the peripheral device. When the CPU needs to perform an inquiring process to wait for a peripheral device to come to an expected state, an inquiring apparatus is activated, instead of the CPU, to perform an inquiring process. The CPU is placed in a power-saving state which stops outputting the clock to the CPU when the inquiring apparatus performs the inquiring process. The inquiring process includes outputting a read cycle to the peripheral device receiving a current state of the peripheral device in response to the read cycle; and comparing the current state with the expected state. If the current state and the expected state are the same, the clock is outputted to the CPU again.

Claims

1. An inquiring apparatus, provided in an electronic apparatus having a central processor unit (CPU), the electronic apparatus comprising a clock controller, and a main bus, the inquiring apparatus comprising:

a multiplexer for selectively coupling a first bus or a second bus with the main bus,

peripheral device associated with an address;

wherein when the CPU needs to wait for the peripheral device coupled to the main bus to come to an expected state, the CPU activates the inquiring apparatus to inform an awakening unit of the address of the peripheral device and to make the multiplexer couple the second bus with the main bus so that the awakening unit, instead of the CPU, repeatedly inquires the current state of the peripheral device associated with the address to determine whether the current state of the peripheral device agrees with the expected state and so that the CPU is placed into a power-saving state in which the clock controller stops outputting a clock to the CPU.

2. The inquiring apparatus according to claim 1, wherein when the current state agrees with the expected state, the awakening unit outputs an awakening signal to the clock controller.

3. The inquiring apparatus according to claim 2, wherein after receiving the awakening signal, the clock controller outputs the clock to the CPU again.

4. The inquiring apparatus according to claim 2, wherein the awakening unit comprises:

an address register for storing the address of the peripheral device;

a state register for storing the expected state of the peripheral device;

a bus interface coupled to the second bus for providing a read cycle according to the address and receiving the current state responded by the peripheral device; and

a comparator for comparing the current state with the expected state and accordingly outputting the awakening signal.

5. The inquiring apparatus according to claim 4, wherein when the CPU enables the awakening unit, the CPU stores the address of the peripheral device in the address register, and stores the expected state in the state register.

6. The inquiring apparatus according to claim 1, wherein when the CPU is not required to wait for the peripheral device to come to the expected state, the multiplexer couples the first bus with the main bus.

7. An inquiring method, for assisting a CPU to repeatedly inquire a peripheral device, the method comprising steps of:

when the CPU needs to perform an inquiring process to wait for the peripheral device to come to an expected state, activating an inquiring apparatus, instead of the CPU, to perform an inquiring process;

placing the CPU in a power-saving state which stops outputting a clock to the CPU when the inquiring apparatus performs the inquiring process;

wherein the inquiring process comprises;

outputting a read cycle to the peripheral device to inquire a current state of the peripheral device;

receiving the current state of the peripheral device in response to the read cycle; and

comparing the current state with the expected state.

8. The inquiring method according to claim 7, wherein when the inquiring process performed by the inquiring apparatus determines that the current state agrees with the expected state, the awakening unit enables the clock controller to output the clock to the CPU again.

9. An electronic apparatus comprising:

a processor;

a clock controller;

an inquiring apparatus comprising;

an awakening unit, which is activated instead of the processor to inquire a current state of a peripheral device associated with an address on a main bus when the processor activates the inquiring apparatus to inform the awakening unit of the address of the peripheral device;

a multiplexer for selectively coupling one of the processor and the awakening unit to the main bus; and

wherein when the processor needs to wait for a peripheral device coupled to the main bus to come to an expected state, the processor activates the inquiring apparatus to inform the awakening unit of the address of the peripheral device and to make the multiplexer couple the awakening unit to the main bus so that the awakening unit, instead of the processor, repeatedly inquires the current state of the peripheral device associated with the address to determine whether the current state of peripheral device agrees with the expected state and so that the processor is placed into a power-saving state in which the clock controller stops outputting a clock to the processor.

10. The electronic apparatus according to claim 9, when the processor needs to wait for the peripheral device coupled to the main bus to come to the expected state, the processor stores the address of the peripheral device in the awakening unit to activate the inquiring apparatus.

11. The electronic apparatus according to claim 9, when the processor needs to wait for the peripheral device coupled to the main bus to come to the expected state, the processor stores the expected state in the awakening unit to activate the inquiring apparatus.

12. The electronic apparatus according to claim 9, wherein the awakening unit comprises a bus interface for providing a read cycle according to the address and receiving the current state responded by the peripheral device associated with the address.

13. The electronic apparatus according to claim 12, wherein the awakening unit further comprises:

an address memory for storing the address of the peripheral device;

a state memory for storing the expected state of the peripheral device; and

a comparator for comparing the current state with the expected state and accordingly outputting the awakening signal.

14. The electronic apparatus according to claim 13, when the processor needs to wait for the peripheral device coupled to the main bus to come to the expected state, the processor stores the address of the peripheral device in the awakening unit to activate the inquiring apparatus.

15. The electronic apparatus according to claim 13, when the processor needs to wait for the peripheral device coupled to the main bus to come to the expected state, the processor stores the expected state in the awakening unit to activate the inquiring apparatus.