Method of providing an interface to a plurality of peripheral devices using bus adapter chips

• US 7,263,570 B2
• Filed: 05/03/2006
• Issued: 08/28/2007
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Amdahl, Carlton G., Smith, Dennis H., Schiro, Don, Papa, Stephen E. J., Agneta, Don, Henderson, Michael G.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US11/417,943
• Publication Number:
  US 20060206649A1
• Time in Patent Office: 482 Days
• Field of Search: None
• US Class Current: 710/302
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/328 Computer systems status display G06F11/327 takes precedence
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 21/305 by remotely controlling device operation
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4411 : Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: H02P 7/285 : controlling armature supply only
• CPC Class Codes: H04L 12/12 : Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 41/0213 : Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/0659 : by isolating or reconfiguring faulty entities
• CPC Class Codes: H04L 41/0806 : for initial configuration or provisioning, e.g. plug-and-play
• CPC Class Codes: H04L 41/12 : Discovery or management of network topologies
• CPC Class Codes: H04L 41/22 : comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 43/00 : Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 67/1001 : for accessing one among a plurality of replicated servers
• CPC Class Codes: H05K 7/1492 : having electrical distribution arrangements, e.g. power supply or data communications
• CPC Class Codes: H05K 7/207 : Thermal management, e.g. cabinet temperature control
• CPC Class Codes: H05K 7/20736 : within cabinets for removing heat from server blades
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.

Claims

1. A method of electrically decoupling a central processing unit (CPU) of a server from a plurality of interface modules comprising:

routing an I/O bus having a first format from a central processing unit to primary sides of a plurality of bus adapter chips;

routing an I/O bus of the first format from secondary sides of the bus adapter chips to respective ones of a plurality of interface modules;

resetting the secondary side of at least one bus adapter chip from the central processing unit; and

powering down at least one interface module associated with the secondary side of the at least one bus adapter chip when the secondary side of the bus adapter chip is reset, wherein the bus adapter chip provides electrical termination for the central processing unit when the interface module is powered down.

2. The method of claim 1, wherein the bus adapter chips comprise electrical hardware which provides arbitered access along the I/O busses.

3. The method of claim 1, further including mounting a plurality of interface cards in interface card slots in the plurality of interface modules.

4. The method of claim 1, further including removably mounting the interface modules on a chassis.

5. The method of claim 4, wherein removably mounting the interface module comprises mounting the interface module such that the interface module may be removed from the chassis and disconnected electrically from the CPU or mounted on the chassis and connected electrically to the CPU without powering down the CPU.

6. The method of claim 1, wherein the at least one bus adapter chip comprises electrical hardware providing arbitered access and speed matching along the I/O busses.

7. The method of claim 1, wherein the I/O busses comprise peripheral component interconnect (PCI) busses.

8. The method of claim 1, further comprising restoring power to the at least one interface module associated with the secondary side of the at least one bus adapter chip and bringing the at least one bus adapter chip out of reset after restoring power to the interface module.

9. A system for electrically decoupling a central processing unit (CPU) of a server from a plurality of interface modules comprising:

means for routing an I/O bus having a first format from a central processing unit to primary sides of a plurality of bus adapter chips;

means for routing an I/O bus of the first format from secondary sides of the bus adapter chips to respective ones of a plurality of interface modules;

means for resetting the secondary side of at least one bus adapter chip from the central processing unit; and

means for powering down at least one interface module associated with the secondary side of the at least one bus adapter chip when the secondary side of the at least one bus adapter chip is reset, wherein the bus adapter chip provides electrical termination for the central processing unit when the interface module is powered down.

10. The system of claim 9, wherein the bus adapter chips comprise electrical hardware which provides arbitered access along the I/O busses.

11. The system of claim 9, wherein the means for routing the I/O buses to and from bus adapter chips comprises means for electrically isolating the CPU from electrical disruption when one of the interface modules is removed.

12. The system of claim 9, further including means for mounting a plurality of interface cards in interface card slots in the plurality of interface modules.

13. The system of claim 9, further including means for removably mounting the interface modules on a chassis.

14. The method of claim 9, further comprising means for restoring power to the at least one interface module associated with the secondary side of the at least one bus adapter chip and means for bringing the at least one bus adapter chip out of reset after restoring power to the interface module.

15. A method of electrically decoupling at least one of a plurality of interface modules to a central processing unit (CPU) such that the at least one of the interface modules can be disconnected without powering down the remaining interface modules or the CPU, the method comprising:

mounting a CPU on a chassis;

removably mounting a plurality of interface modules to the chassis;

mounting a backplane printed circuit board on the chassis, wherein the backplane printed circuit board comprises at least one bus adapter chip for each of the plurality of interface modules, and wherein each bus adapter chip has a primary side and a secondary side,

routing an I/O bus on the backplane printed circuit board from the primary side of the at least one bus adapter chip to the CPU; and

routing an I/O bus on the backplane printed circuit board from the secondary side of the at least one bus adapter chip to the corresponding one of the interface modules;

resetting the secondary side of at least one bus adapter chip from the CPU, wherein the at least one bus adapter chip provides electrical termination for the CPU when the interface module is powered down and when the secondary side of the at least one bus adapter chip is reset.

16. The method of claim 15, wherein the at least one bus adapter chip comprises electrical hardware providing arbitered access and speed matching along the I/O busses.

17. The method of claim 15, wherein the I/O busses comprise peripheral component interconnect (PCI) busses.

18. The method of claim 15, wherein removably mounting the plurality of interface modules to the chassis comprises:

connecting a 180 pin female connector on the backplane printed circuit board with a 180 pin male connector on a interface module of the plurality of interface modules; and

connecting a 360 pin female connector on the backplane printed circuit board with a 360 pin male connector on the CPU.

19. The method of claim 15, further including mounting a plurality of interface cards in interface card slots in the plurality of interface modules.

20. The method of claim 19, wherein the backplane printed circuit board powers down the interface modules including the interface cards thereon.