LSI, test pattern generating method for scan path test, LSI inspecting method, and multichip module

• US 7,263,640 B2
• Filed: 12/05/2005
• Issued: 08/28/2007
• Est. Priority Date: 12/13/2004
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kobayashi, Takuya
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US11/293,166
• Publication Number:
  US 20060125466A1
• Time in Patent Office: 631 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Registers 119 and 120 for power control or power-off signals in an LSI are set as a dedicated chain and a control signal can be controlled desirably from the outside so that the states of the registers 119 and 120 can be monitored easily. In a test pattern generating method for a scan path test, the relation between values of the registers for the power control or power-off and power supplies to be controlled is set as an option in order to control the registers 119 and 120 for the power control or power-off. In this manner, a pattern in which the power control function or the power-off function of the LSI is taken into consideration can be produced.

Claims

1. An LSI having a power control function or a power-off function, comprising:

power terminals;

ground terminals;

registers, connected as a scan chain and capable of holding power control information;

a gate circuit, capable of controlling a clock signal to be supplied to the registers;

a clock control terminal capable of inputting a control signal for controlling the gate circuit;

scan-in terminals capable of inputting scan signals; and

scan-out terminals capable of outputting the scan signals;

wherein;

the control signal is supplied from the outside and the scan signals are monitored during a structured test.

2. The LSI according to claim 1, further comprising:

a power control module for power control or power-off;

wherein;

the LSI can be inspected in a power control state or a power-off state by controlling the power control module during the structured test.

3. A method for inspecting an LSI including power terminals, ground terminals, registers connected as a scan chain and capable of holding power control information, a gate circuit capable of controlling a clock signal to be supplied to the registers, a clock control terminal capable of inputting a control signal for controlling the gate circuit, scan-in terminals capable of inputting scan signals, and scan-out terminals capable of outputting the scan signals;

the method comprising the step of;

inspecting the LSI in a power control state or a power-off state on the basis of a test pattern for inspecting a power control function or a power-off function of the LSI.

4. The method for inspecting an LSI according to claim 3, wherein the LSI is inspected by detecting an expected value corresponding to the power control information during a structured test.

5. The method for inspecting an LSI according to claim 4, including an LSI inspection apparatus having:

a power supply connected to the power terminals and the ground terminals so as to be capable of supplying power to the LSI;

a signal driver connected to the scan-in terminals so as to be capable of supplying the scan signals to the scan-in terminals; and

a signal comparator connected to the scan-out terminals so as to be capable of detecting the scan signals from the scan-out terminals.

6. The method for inspecting an LSI according to claim 4, including:

a power supply module connected to the power terminals and the ground terminals so as to be capable of supplying power to the LSI;

an LSI inspection board mounted with the power supply module and the LSI; and

an LSI inspection apparatus having a power supply capable of supplying power to the power supply module, a signal driver connected to the scan-in terminals so as to be capable of supplying the scan signals to the scan-in terminals, and a signal comparator connected to the scan-out terminals so as to be capable of detecting the scan signals from the scan-out terminals.

7. A multichip module, comprising:

an LSI having power terminals;

ground terminal;

registers connected as a scan chain and capable of holding power control information;

a gate circuit capable of controlling a clock signal to be supplied to the registers;

a clock control terminal capable of inputting a control signal for controlling the gate circuit;

scan-in terminals capable of inputting scan signals; and

scan-out terminals capable of outputting the scan signals;

a power supply module for performing power control or power-off on the LSI; and

a package on which the LSI and the power supply module are mounted;

wherein the LSI can be inspected in a power control state or a power-off state by controlling the power supply module in the multichip module during a structured test.