Apparatus and method for accommodating loss of signal

• US 7,263,648 B2
• Filed: 01/24/2003
• Issued: 08/28/2007
• Est. Priority Date: 01/24/2003
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Wegener Communications, Inc. (Wegener Corporation)
• Inventors: Osburn, Kenneth, Blackburn, Dennis, Tan, Weihong, Buggy, Robert
• Primary Examiner(s): Kerveros; James C
• Application Number:
  US10/350,930
• Publication Number:
  US 20040148555A1
• Time in Patent Office: 1,677 Days
• Field of Search: 714/718, 714/763, 725/68, 365/230.08, 710/52
• US Class Current: 714/763
• CPC Class Codes: H04H 20/38 Arrangements for distribution where lower stations, e.g. receivers, interact with the broadcast
• CPC Class Codes: H04H 60/06 Arrangements for scheduling broadcast services or broadcast-related services
• CPC Class Codes: H04H 60/12 wherein another information is substituted for the portion of broadcast information
• CPC Class Codes: H04H 60/27 Arrangements for recording or accumulating broadcast information or broadcast-related information
• CPC Class Codes: H04N 21/4331 Caching operations, e.g. of an advertisement for later insertion during playback
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/44016 involving splicing one content stream with another content stream, e.g. for substituting a video clip
• CPC Class Codes: H04N 21/4425 Monitoring of client processing errors or hardware failure
• CPC Class Codes: H04N 21/812 involving advertisement data advertising per se G06Q30/02
• CPC Class Codes: H04N 7/162 Authorising the user terminal, e.g. by paying; Registering the use of a subscription channel, e.g. billing

Abstract

A memory control system for a network that broadcasts to multiple terminals content data including music, video and the like, and also including commercial advertisements. A memory in the terminal unit stores content data that is played upon a loss of signal from the broadcast network. The memory also stores commercial advertisements for playback from the terminal memory according to schedule control instructions, which are also stored in a memory at the terminal unit. Writing of content to a memory and reading content from the memory may be executed concurrently by interleaving. A microprocessor arbitrates use of input, output and memory buffers such that reading content from memory provides content output maintaining uninterrupted real time play even when new content data is being stored concurrently. Content data memory addresses are stored in sector tables that are further arranged in File Allocation Tables in a second memory.

Claims

1. A memory control system for network distributed content data comprising:

an input buffer;

an output buffer;

a first memory storing content data;

a second memory for storing File Allocation Tables and control instructions;

a read/write control data structure that interleaves

reading content data to be played from said first memory into said input buffer and out to said output buffer and from said output buffer to an output device, with

writing content data to be stored into said input buffer and to said output buffer and from said output buffer to said first memory,

wherein said content data to be stored to said first memory is stored in an amount corresponding to a preconfigured duration of playing time; and

wherein said memory control system provides a data output that maintains uninterrupted real time play.

2. The memory control system of claim 1 wherein said input buffer, said output buffer, and said control data structure are embodied in at least one integrated circuit selected from the group consisting of:

a Field Programmable Gate Array, a Configurable System on a Chip, a System on a Chip and an Application Specific Integrated Circuit.

3. The memory control system of claim 1 wherein said input buffer, said output buffer, said control data structure, said first memory storing content data and said second memory are an option card that operatively communicates with a receiver/decoder.

4. The memory control system of claim 3 further comprising a separate output from an output in said receiver/decoder.

5. The memory control system of claim 1 wherein said content data is music data encoded according to an MPEG protocol.

6. The memory control system of claim 1 wherein said content data is video data encoded according to an MPEG protocol.

7. The memory control system of claim 1 wherein said content data to be stored is periodically refreshed.

8. A memory control system for a broadcast content network receiver comprising:

a configurable system on a chip comprising;

an input buffer,

an output buffer,

a microprocessor;

a first flash memory;

a second flash memory;

said configurable system on a chip being configured to play current content data on a first channel and to monitor said play of said current content data for loss of signal;

said configurable system on a chip also being configured to receive on a second channel content data for storage, said first flash memory storing said content data for storage and said second flash memory storing address information for said content data for storage;

said configurable system on a chip also being configured to play said content data for storage from said first flash memory;

wherein said play and said storage of said content data for storage may be executed concurrently such that stored content data output maintains uninterrupted real time play.

9. The memory control system of claim 8, wherein said content data for storage is back up content.

10. The memory control system of claim 9, wherein said configurable system on a chip monitors said play of said current content data for loss of signal by testing the duration and error rate of said signal.

11. The memory control system of claim 8, wherein said content data for storage is commercial content data.

12. The memory control system of claim 8 wherein said content data for storage is played upon a loss of a signal carrying said current content data.

13. The memory control system of claim 8 further comprising a data structure for reacquiring said signal after said loss of signal.

14. The memory control system of claim 13 wherein said data structure for reacquiring said signal after said loss of signal tests an initial reacquisition of said signal for duration and error rate.

15. The memory control system of claim 8 further comprising a parallel/serial shift register for output.

16. A receiver for network distributed content data comprising:

an input buffer;

an output buffer;

a first memory, said first memory being configured to store content data;

a second memory, said second memory being configured to store at least one File Allocation Table and to store at least one control instruction; and

a processor, said processor being in operative communication with said input buffer, said output buffer, said first memory and said second memory, and said processor being configured to interleave

a reading of content data to be played from said first memory into said input buffer and out to said output buffer and from said output buffer to an output device, with

a writing of content data to be stored into said input buffer and to said output buffer and from said output buffer to said first memory,

wherein said content data to be stored to said first memory is stored in an amount corresponding to a preconfigured duration of playing time; and

wherein said memory control system provides a data output that maintains uninterrupted real time play.

17. A memory control system for a broadcast content network receiver comprising:

a configurable system on a chip comprising;

an input buffer,

an output buffer,

a microprocessor;

a first flash memory;

a second flash memory;

a sector table, said sector table being configured to hold addresses corresponding to a location in said first flash memory for each of a plurality of sectors of said content data;

a header byte, said header byte being associated with said sector table and said header byte indicating that said sector table is valid or invalid;

a first file allocation table, said first file allocation table being in said second memory, said first file allocation table having a marker byte, said marker byte indicating that said file allocation table is valid or invalid, said first file allocation table being configured to receive an allocation of said sector table;

said configurable system on a chip being configured to play current content data on a first channel and to monitor said play of said current content data for loss of signal;

said configurable system on a chip also being configured to receive on a second channel content data for storage, said first flash memory storing said content data for storage and said second flash memory storing address information for said content data for storage;

said configurable system on a chip also being configured to play said content data for storage from said first flash memory;

wherein said play and said storage of said content data for storage are interleavable in that said play and said storage may be executed concurrently such that stored content data output maintains uninterrupted real time play.

18. The memory control system of claim 17 wherein said configurable system on a chip is configured to receive a call up instruction for playing a particular portion of content data;

and

being further configured to read said first file allocation table marker byte; and

being further configured to read said sector table in said first file allocation table if said file allocation table marker byte is valid; and

being further configured to call or play said multiple sectors from said first memory that correspond to said particular portion of content data if said header byte of said sector table is valid and if said header byte identifies said one of said sector tables as corresponding to said particular portion of content data.

19. The memory control system of claim 17 wherein said configurable system on a chip is further configured to check said file allocation table for invalid sector tables;

and

said configurable system on a chip being further configured to write said sector tables that are valid according to said header bytes to a second file allocation table in a second memory when an invalid sector table is discovered; and

said configurable system on a chip being further configured to erase said first file allocation table.

20. The memory control system of claim 17 wherein said system is configured to execute periodically.

21. The memory control system of claim 17 wherein said system is configured to execute in response to a discarding of any content data.

22. The memory control system of claim 17 wherein said invalid designation in said marker byte is a designation selected from the group consisting of:

being blank, being written, being checked for errors and being discarded.

23. The memory control system of claim 17 wherein said invalid designation in said header byte is a designation selected from the group consisting of:

being blank, being written, being checked for errors and being discarded.

24. A memory control system for network distributed content data comprising:

an input buffer;

an output buffer;

a first memory;

a sector table, said sector table being configured to hold addresses corresponding to a location in said first memory for each of a plurality of sectors of content data;

a header byte, said header byte being associated with said sector table and said header byte indicating that said sector table is valid or invalid;

a second memory for storing at least one file allocation table and control instructions, wherein said at least one file allocation table has a marker byte, said marker byte indicating that said at least one file allocation table is valid or invalid, said at least one file allocation table being configured to receive an allocation of said sector table;

a read/write control data structure that interleaves

reading content data to be played from said first memory into said input buffer and out to said output buffer and from said output buffer to an output device, with

writing content data to be stored into said input buffer and to said output buffer and from said output buffer to said first memory.