Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 7,265,000 B2
• Filed: 02/14/2006
• Issued: 09/04/2007
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek
• Primary Examiner(s): Vu; David
• Application Number:
  US11/354,470
• Publication Number:
  US 20060134837A1
• Time in Patent Office: 567 Days
• Field of Search: 438128-132, 438/197, 438/210, 438/467, 438/600, 438/601, 257/50, 257/530, 257/E23.147, 257/E23.149
• US Class Current: 438/131
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A process for fabricating a cell in a 3-D semiconductor memory device comprising:

forming a first conductor layer;

forming a first semiconductor layer overlying the conductor layer;

oxidizing at least a portion of the first semiconductor layer in a plasma to form an oxide layer thereon;

forming a second semiconductor layer overlying the oxide layer;

sequentially etching the second semiconductor layer, the oxide layer, the first semiconductor layer and the first conductor layer to form a line;

forming a second conductor layer overlying the line; and

sequentially etching the second conductor layer and the line to form a pillar of the 3-D semiconductor memory device, wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another.

2. The process of claim 1, wherein the step of oxidizing at least a portion of the first semiconductor layer comprises plasma oxidation at a temperature of no more than about 400°

C.

3. The process of claim 1, wherein the step of forming a first conductor layer comprises forming a conductor layer including metal elements, and wherein the step of oxidizing at least a portion of the first semiconductor layer comprises a plasma oxidation process carried out at a temperature below that at which the metal elements can interdiffuse in the conductor layer.

4. The process of claim 3, wherein the step of forming a conductor layer containing metal elements comprises forming a refractory metal.

5. The process of claim 3, wherein the step of forming a conductor layer containing metal elements comprises forming a refractory metal silicide.

6. The process of claim 1, wherein the step of sequential etching comprises forming edge regions on the pillar, and wherein the process further comprises oxidizing the edge region using a plasma oxidation process.

7. The process of claim 1, wherein the step of forming a first semiconductor layer comprises forming a layer of polycrystalline silicon doped with a conductivity determining dopant.

8. The process of claim 1, wherein the step of forming a first semiconductor layer comprises forming a layer of amorphous silicon.

9. The process of claim 1, wherein the step of forming a first semiconductor layer comprises forming a layer of recrystallized silicon.

10. A process for fabricating a cell in a 3-D semiconductor memory device comprising:

forming a first conductor layer;

forming a first semiconductor layer overlying the first conductor layer;

oxidizing at least a portion of the first semiconductor layer to form an oxide layer thereon;

forming a second semiconductor layer overlying the oxide layer;

sequentially etching the second semiconductor layer, the oxide layer, the first semiconductor layer, the first conductor layer to form a line;

forming a second conductor layer overlying the first line;

etching the second conductor layer to form a second line orthogonal to the first line and etching the first line to form a pillar; and

forming edge regions on the pillar using a plasma oxidation process;

wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another.