Post passivation interconnection schemes on top of the IC chips
First Claim
Patent Images
1. A method for fabricating a circuit component comprising:
- providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a damascene process; and
forming a passive device over said passivation layer, wherein said forming said passive device comprises;
depositing a first metal layer over said passivation layer,after said depositing said first metal layer, forming a patterned photoresist layer,after said forming said patterned photoresist layer, electroplating a second metal layer,after said electroplating said second metal layer, removing said patterned photoresist layer, andafter said removing said patterned photoresist layer, etching said first metal layer.
4 Assignments
0 Petitions
Accused Products
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
-
Citations
19 Claims
-
1. A method for fabricating a circuit component comprising:
-
providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a damascene process; and forming a passive device over said passivation layer, wherein said forming said passive device comprises; depositing a first metal layer over said passivation layer, after said depositing said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for fabricating a circuit component comprising:
-
providing a semiconductor substrate, a metallization structure over said semiconductor substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a damascene process; and forming an inductor over said passivation layer, wherein said forming said inductor comprises; depositing a first metal layer over said passivation layer, after said depositing said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
Specification