Thin-film transistor with vertical channel region
First Claim
1. A vertical thin film transistor (V-TFT), the transistor comprising:
- a substrate;
a substrate insulation layer overlying the substrate;
a gate, having sidewalls and a top surface, overlying the substrate insulation layer;
a gate insulation layer overlying the gate top surface;
a first source/drain region overlying the gate insulation layer;
a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall;
a channel region overlying the first gate sidewall, interposed between the first and second source/drain regions;
a Vt adjust implant in the channel region; and
,wherein the first and second source/drain regions are crystallized Si having a thickness in the range of 300 to 1000 Å
.
1 Assignment
0 Petitions
Accused Products
Abstract
A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
-
Citations
14 Claims
-
1. A vertical thin film transistor (V-TFT), the transistor comprising:
-
a substrate; a substrate insulation layer overlying the substrate; a gate, having sidewalls and a top surface, overlying the substrate insulation layer; a gate insulation layer overlying the gate top surface; a first source/drain region overlying the gate insulation layer; a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; a channel region overlying the first gate sidewall, interposed between the first and second source/drain regions; a Vt adjust implant in the channel region; and
,wherein the first and second source/drain regions are crystallized Si having a thickness in the range of 300 to 1000 Å
. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
Specification